The design of multimedia platforms is becoming increasingly more complex. Modern multimedia systems need to support a large number of applications or functions in a single device. To achieve high performance in such systems, more and more processors are being integrated into a single chip to build Multi-Processor Systems-on-Chip (MPSoCs). The heterogeneity of such systems is also increasing with the use of specialized digital hardware, application domain processors and other IP (intellectual property) blocks on a single chip, since various standards and algorithms are to be supported. These embedded systems also need to meet timing and other non-functional constraints like low power and design area. Further, processors designed for multimedia applications (also known as streaming processors) often do not support preemption to keep costs low, making traditional analysis techniques unusable. To achieve high performance in such systems, the limited computational resources must be shared. The concurrent execution of dynamic applications on shared resources causes interference. The fact that these applications do not always run concurrently only adds a new dimension to the design problem. We define each such combination of applications executing concurrently as a usecase. Currently, companies often spend 60-70% of the product development cost in verifying all feasible use-cases. Having an analysis technique can significantly reduce this development cost. Since applications are often added to the system at run-time (for example, a mobile-phone user may download a Java application at run-time), a complete analysis at design-time is also not feasible. Existing techniques are unable to handle this dynamism, and the only solution left to the designer is to over-dimension the hardware by a large factor leading to increased area, cost and power. In this thesis, a run-time performance prediction methodology is presented that can accurately and quickly predict the performance of multiple applications before they execute in the system. Synchronous data flow (SDF) graphs are used to model applications, since they fit well with characteristics of multimedia applications, and at the same time allow analysis of application performance. Further, their atomic execution requirement matches well with the non-preemptive nature of many streaming processors. While a lot of techniques are available to analyze performance of single applications, for multiple applications this task is a lot harder and little work has been done in this direction. This thesis presents one of the first attempts to analyze performance of multiple applications executing on heterogeneous non-preemptive multiprocessor platforms. Our technique uses performance expressions computed off-line from the application specifications. A run-time iterative probabilistic analysis is used to estimate the time spent by tasks during the contention phase, and thereby predict the performance of applications. An admission controller is presented using this analysis technique. The controller admits incoming applications only if their performance is expected to meet their desired requirements. Further, we present a design-flow for designing systems with multiple applications. A hybrid approach is presented where the time-consuming applicationspecific computations are done at design-time, and in isolation with other applications, and the use-case-specific computations are performed at run-time. This allows easy addition of applications at run-time. A run-time mechanism is presented to manage resources in a system. This ensures that once an application is admitted in the system, it can meet its performance constraints. This mechanism enforces budgets and suspends applications if they achieve a higher performance than desired. A resource manager (RM) is presented to manage computation and communication resources, and to achieve the above goals of performance prediction, admission control and budget enforcement. With high consumer demand the time-to-market has become significantly lower. To cope with the complexity in designing such systems, a largely automated design-flow is needed that can generate systems from a high-level architectural description such that they are not error-prone and consume less time. This thesis presents a highly automated flow – MAMPS (Multi-Application Multi-Processor Synthesis), that synthesizes multi-processor platforms for multiple applications specified in the form of SDF graph models. Another key design automation challenge is fast exploration of software and hardware implementation alternatives with accurate performance evaluation, also known as design space exploration (DSE). This thesis presents a design methodology to generate multiprocessor systems in a systematic and fully automated way for multiple use-cases. Techniques are presented to merge multiple use-cases into one hardware design to minimize cost and design time, making it well-suited for fast DSE of MPSoC systems. Heuristics to partition use-cases are also presented such that each partition can fit in an FPGA, and all use-cases can be catered for. The above tools are made available on-line for use by the research community. The tools allow anyone to upload their application descriptions and generate the FPGA multi-processor platform in seconds.
|Qualification||Doctor of Philosophy|
|Award date||28 Apr 2009|
|Place of Publication||Eindhoven|
|Publication status||Published - 2009|