Analog IC having test arrangement and test method for such an IC

A. Zjajo (Inventor), H.J. Bergveld (Inventor), R.F. Schuttert (Inventor), J. Pineda de Gyvez (Inventor)

Research output: PatentPatent publication

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Abstract

An integrated circuit (IC) comprises a plurality of analog stages (10a-c), each of the analog stages being conductively coupled to a power supply (20; 20a-c), and being conductively coupled to each other by a signal path (12); and a test arrangement for testing the plurality of analog stages, the test arrangement comprising input means such as an analog bus (40) coupled to a signal path input of each analog stage from the plurality of analog stages, output means such as a further analog bus (50) for communicating a test result to an output of the integrated circuit, switching means such as a plurality of switches (36) in the biasing infrastructure of the IC for selectively disabling an analog stage, and control means such a shift register (60) for controlling the switching means.; Consequently, the analog stages of the IC can be tested and debugged in isolation without the need for switches in the signal path through the cores. A current sensor (70) may be present in the power supply to facilitate structural testing of the analog stages in isolation.
Original languageEnglish
Patent numberWO2007049210
Publication statusPublished - 3 May 2007

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