This paper presents a method for the on-chip measurement and correction of gain errors, offsets and time-skew errors in time-interleaved ADC's. With the proposed method, the errors can be measured and processed in the digital domain. Then, this information is used to optimize several digitally controlled analog parameters of the circuit, that minimize the effect of aforementioned mismatch errors. After optimization, the digital logic can be switched off completely in order to save power. Simulation results on a full-transistor implementation of the time-interleaved sampling structure show that the channel matching errors can be accurately compensated.
|Title of host publication||European Conference on Circuit Theory and Design 2007, ECCTD 2007|
|Number of pages||4|
|Publication status||Published - 2007|
|Event||European Conference on Circuit Theory and Design 2007, ECCTD 2007 - Seville, Spain|
Duration: 26 Aug 2007 → 30 Aug 2007
|Conference||European Conference on Circuit Theory and Design 2007, ECCTD 2007|
|Period||26/08/07 → 30/08/07|