Analog calibration of channel mismatches in time-interleaved ADCs

Pieter Harpe; Hans Hegt; Arthur Van Roermund

doi:10.1109/ECCTD.2007.4529580

Analog calibration of channel mismatches in time-interleaved ADCs

Pieter Harpe, Hans Hegt, Arthur Van Roermund

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › Academic › peer-review

2 Citations (Scopus)

Abstract

This paper presents a method for the on-chip measurement and correction of gain errors, offsets and time-skew errors in time-interleaved ADC's. With the proposed method, the errors can be measured and processed in the digital domain. Then, this information is used to optimize several digitally controlled analog parameters of the circuit, that minimize the effect of aforementioned mismatch errors. After optimization, the digital logic can be switched off completely in order to save power. Simulation results on a full-transistor implementation of the time-interleaved sampling structure show that the channel matching errors can be accurately compensated.

Original language	English
Title of host publication	European Conference on Circuit Theory and Design 2007, ECCTD 2007
Pages	236-239
Number of pages	4
DOIs	https://doi.org/10.1109/ECCTD.2007.4529580
Publication status	Published - 2007
Event	European Conference on Circuit Theory and Design 2007, ECCTD 2007 - Seville, Spain Duration: 26 Aug 2007 → 30 Aug 2007

Conference

Conference	European Conference on Circuit Theory and Design 2007, ECCTD 2007
Country	Spain
City	Seville
Period	26/08/07 → 30/08/07

Access to Document

10.1109/ECCTD.2007.4529580

Link to publication in Scopus

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title = "Analog calibration of channel mismatches in time-interleaved ADCs",

abstract = "This paper presents a method for the on-chip measurement and correction of gain errors, offsets and time-skew errors in time-interleaved ADC's. With the proposed method, the errors can be measured and processed in the digital domain. Then, this information is used to optimize several digitally controlled analog parameters of the circuit, that minimize the effect of aforementioned mismatch errors. After optimization, the digital logic can be switched off completely in order to save power. Simulation results on a full-transistor implementation of the time-interleaved sampling structure show that the channel matching errors can be accurately compensated.",

author = "Pieter Harpe and Hans Hegt and {Van Roermund}, Arthur",

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doi = "10.1109/ECCTD.2007.4529580",

language = "English",

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AU - Hegt, Hans

AU - Van Roermund, Arthur

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N2 - This paper presents a method for the on-chip measurement and correction of gain errors, offsets and time-skew errors in time-interleaved ADC's. With the proposed method, the errors can be measured and processed in the digital domain. Then, this information is used to optimize several digitally controlled analog parameters of the circuit, that minimize the effect of aforementioned mismatch errors. After optimization, the digital logic can be switched off completely in order to save power. Simulation results on a full-transistor implementation of the time-interleaved sampling structure show that the channel matching errors can be accurately compensated.

AB - This paper presents a method for the on-chip measurement and correction of gain errors, offsets and time-skew errors in time-interleaved ADC's. With the proposed method, the errors can be measured and processed in the digital domain. Then, this information is used to optimize several digitally controlled analog parameters of the circuit, that minimize the effect of aforementioned mismatch errors. After optimization, the digital logic can be switched off completely in order to save power. Simulation results on a full-transistor implementation of the time-interleaved sampling structure show that the channel matching errors can be accurately compensated.

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DO - 10.1109/ECCTD.2007.4529580

M3 - Conference contribution

SN - 1424413427

SN - 9781424413423

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EP - 239

BT - European Conference on Circuit Theory and Design 2007, ECCTD 2007

T2 - European Conference on Circuit Theory and Design 2007, ECCTD 2007

Y2 - 26 August 2007 through 30 August 2007

ER -