Analog calibration of channel mismatches in time-interleaved ADCs

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2 Citations (Scopus)

Abstract

This paper presents a method for the on-chip measurement and correction of gain errors, offsets and time-skew errors in time-interleaved ADC's. With the proposed method, the errors can be measured and processed in the digital domain. Then, this information is used to optimize several digitally controlled analog parameters of the circuit, that minimize the effect of aforementioned mismatch errors. After optimization, the digital logic can be switched off completely in order to save power. Simulation results on a full-transistor implementation of the time-interleaved sampling structure show that the channel matching errors can be accurately compensated.

Original languageEnglish
Title of host publicationEuropean Conference on Circuit Theory and Design 2007, ECCTD 2007
Pages236-239
Number of pages4
DOIs
Publication statusPublished - 2007
EventEuropean Conference on Circuit Theory and Design 2007, ECCTD 2007 - Seville, Spain
Duration: 26 Aug 200730 Aug 2007

Conference

ConferenceEuropean Conference on Circuit Theory and Design 2007, ECCTD 2007
CountrySpain
CitySeville
Period26/08/0730/08/07

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