Analog automatic test pattern generation for quasi-static structural test.

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A new approach for structural, fault-oriented analog test generation methodology to test for the presence of manufacturing-related defects is proposed. The output of the test generator consists of optimized test stimuli, fault coverage and sampling instants that are sufficient to detect the failure modes in the circuit under test. The tests are generated and evaluated on a multistep ADC taking into account the potential fault masking effects of process spread on the faulty circuit responses. Similarly, the test generator results offer indication for the circuit partitioning within the framework of circuit performance, area and testability.
Original languageEnglish
Pages (from-to)1383-1391
Number of pages9
JournalIEEE Transactions on Very Large Scale Integration (VLSI) Systems
Issue number17
Publication statusPublished - 2009


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