An UWB, low-noise, low-power quadrature VCO using delay-locked loop in 40-nm CMOS for image-rejection receivers

P. Kaul; H. Gao; Xin He; P.G.M. Baltus

doi:10.1109/ISCAS.2018.8350984

An UWB, low-noise, low-power quadrature VCO using delay-locked loop in 40-nm CMOS for image-rejection receivers

P. Kaul, H. Gao, Xin He, P.G.M. Baltus

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › Academic › peer-review

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Abstract

This paper presents a quadrature voltage controlled oscillator (QVCO) with the delay-locked loop (DLL) for ultra wideband (UWB) application. A new architecture of delay-locked loop is presented to achieve low power consumption and low-noise operation. A system analysis of delay locked loop based QVCO is discussed including the transfer function and the stability. Also, this DLL architecture is implemented in a 40-nm CMOS technology. From the simulated result, this design achieves 40% delay range from 6-9 GHz, with -149.1 dBc/Hz phase noise at 100 MHz frequency offset. The power consumption is 11 mW, and the phase accuracy is less than 5°.

Original language	English
Title of host publication	2018 IEEE International Symposium on Circuits and Systems, ISCAS 2018 - Proceedings
Place of Publication	Piscataway
Publisher	Institute of Electrical and Electronics Engineers
Number of pages	5
ISBN (Electronic)	978-1-5386-4881-0
ISBN (Print)	978-1-5386-4882-7
DOIs	https://doi.org/10.1109/ISCAS.2018.8350984
Publication status	Published - 26 Apr 2018
Event	2018 IEEE International Symposium on Circuits and Systems, ISCAS 2018 - Florence Conference Center, Florence, Italy Duration: 27 May 2018 → 30 May 2018 https://ieeexplore.ieee.org/xpl/mostRecentIssue.jsp?punumber=8334884

Conference

Conference	2018 IEEE International Symposium on Circuits and Systems, ISCAS 2018
Abbreviated title	ISCAS 2018
Country	Italy
City	Florence
Period	27/05/18 → 30/05/18
Internet address	https://ieeexplore.ieee.org/xpl/mostRecentIssue.jsp?punumber=8334884

Keywords

Delay locked loop
Quadrature voltage controlled oscillator
Voltage controlled delay line
UWB
low phase noise
low power

Access to Document

10.1109/ISCAS.2018.8350984

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title = "An UWB, low-noise, low-power quadrature VCO using delay-locked loop in 40-nm CMOS for image-rejection receivers",

abstract = "This paper presents a quadrature voltage controlled oscillator (QVCO) with the delay-locked loop (DLL) for ultra wideband (UWB) application. A new architecture of delay-locked loop is presented to achieve low power consumption and low-noise operation. A system analysis of delay locked loop based QVCO is discussed including the transfer function and the stability. Also, this DLL architecture is implemented in a 40-nm CMOS technology. From the simulated result, this design achieves 40% delay range from 6-9 GHz, with -149.1 dBc/Hz phase noise at 100 MHz frequency offset. The power consumption is 11 mW, and the phase accuracy is less than 5°.",

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Kaul, P , Gao, H, He, X & Baltus, PGM 2018, An UWB, low-noise, low-power quadrature VCO using delay-locked loop in 40-nm CMOS for image-rejection receivers. in 2018 IEEE International Symposium on Circuits and Systems, ISCAS 2018 - Proceedings., 8350984, Institute of Electrical and Electronics Engineers, Piscataway, 2018 IEEE International Symposium on Circuits and Systems, ISCAS 2018, Florence, Italy, 27/05/18. https://doi.org/10.1109/ISCAS.2018.8350984

An UWB, low-noise, low-power quadrature VCO using delay-locked loop in 40-nm CMOS for image-rejection receivers. / Kaul, P.; Gao, H.; He, Xin; Baltus, P.G.M.

2018 IEEE International Symposium on Circuits and Systems, ISCAS 2018 - Proceedings. Piscataway : Institute of Electrical and Electronics Engineers, 2018. 8350984.

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › Academic › peer-review

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