Abstract
This paper presents a quadrature voltage controlled oscillator (QVCO) with the delay-locked loop (DLL) for ultra wideband (UWB) application. A new architecture of delay-locked loop is presented to achieve low power consumption and low-noise operation. A system analysis of delay locked loop based QVCO is discussed including the transfer function and the stability. Also, this DLL architecture is implemented in a 40-nm CMOS technology. From the simulated result, this design achieves 40% delay range from 6-9 GHz, with -149.1 dBc/Hz phase noise at 100 MHz frequency offset. The power consumption is 11 mW, and the phase accuracy is less than 5°.
Original language | English |
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Title of host publication | 2018 IEEE International Symposium on Circuits and Systems, ISCAS 2018 - Proceedings |
Place of Publication | Piscataway |
Publisher | Institute of Electrical and Electronics Engineers |
Number of pages | 5 |
ISBN (Electronic) | 978-1-5386-4881-0 |
ISBN (Print) | 978-1-5386-4882-7 |
DOIs | |
Publication status | Published - 26 Apr 2018 |
Event | 2018 IEEE International Symposium on Circuits and Systems (ISCAS 2018) - Florence Conference Center, Florence, Italy Duration: 27 May 2018 → 30 May 2018 https://ieeexplore.ieee.org/xpl/mostRecentIssue.jsp?punumber=8334884 |
Conference
Conference | 2018 IEEE International Symposium on Circuits and Systems (ISCAS 2018) |
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Abbreviated title | ISCAS 2018 |
Country/Territory | Italy |
City | Florence |
Period | 27/05/18 → 30/05/18 |
Internet address |
Keywords
- Delay locked loop
- Quadrature voltage controlled oscillator
- Voltage controlled delay line
- UWB
- low phase noise
- low power