An UWB, low-noise, low-power quadrature VCO using delay-locked loop in 40-nm CMOS for image-rejection receivers

Research output: Chapter in Book/Report/Conference proceedingConference contributionAcademicpeer-review

Abstract

This paper presents a quadrature voltage controlled oscillator (QVCO) with the delay-locked loop (DLL) for ultra wideband (UWB) application. A new architecture of delay-locked loop is presented to achieve low power consumption and low-noise operation. A system analysis of delay locked loop based QVCO is discussed including the transfer function and the stability. Also, this DLL architecture is implemented in a 40-nm CMOS technology. From the simulated result, this design achieves 40% delay range from 6-9 GHz, with -149.1 dBc/Hz phase noise at 100 MHz frequency offset. The power consumption is 11 mW, and the phase accuracy is less than 5°.

LanguageEnglish
Title of host publication2018 IEEE International Symposium on Circuits and Systems, ISCAS 2018 - Proceedings
Place of PublicationPiscataway
PublisherInstitute of Electrical and Electronics Engineers
Number of pages5
ISBN (Electronic)978-1-5386-4881-0
ISBN (Print)978-1-5386-4882-7
DOIs
StatePublished - 26 Apr 2018
Event2018 IEEE International Symposium on Circuits and Systems, ISCAS 2018 - Florence Conference Center, Florence, Italy
Duration: 27 May 201830 May 2018
https://ieeexplore.ieee.org/xpl/mostRecentIssue.jsp?punumber=8334884

Conference

Conference2018 IEEE International Symposium on Circuits and Systems, ISCAS 2018
Abbreviated titleISCAS 2018
CountryItaly
CityFlorence
Period27/05/1830/05/18
Internet address

Fingerprint

Variable frequency oscillators
Ultra-wideband (UWB)
Electric power utilization
Phase noise
Transfer functions
Systems analysis

Keywords

  • Delay locked loop
  • Quadrature voltage controlled oscillator
  • Voltage controlled delay line
  • UWB
  • low phase noise
  • low power

Cite this

Kaul, P., Gao, H., He, X., & Baltus, P. G. M. (2018). An UWB, low-noise, low-power quadrature VCO using delay-locked loop in 40-nm CMOS for image-rejection receivers. In 2018 IEEE International Symposium on Circuits and Systems, ISCAS 2018 - Proceedings [8350984] Piscataway: Institute of Electrical and Electronics Engineers. DOI: 10.1109/ISCAS.2018.8350984
Kaul, P. ; Gao, H. ; He, Xin ; Baltus, P.G.M./ An UWB, low-noise, low-power quadrature VCO using delay-locked loop in 40-nm CMOS for image-rejection receivers. 2018 IEEE International Symposium on Circuits and Systems, ISCAS 2018 - Proceedings. Piscataway : Institute of Electrical and Electronics Engineers, 2018.
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abstract = "This paper presents a quadrature voltage controlled oscillator (QVCO) with the delay-locked loop (DLL) for ultra wideband (UWB) application. A new architecture of delay-locked loop is presented to achieve low power consumption and low-noise operation. A system analysis of delay locked loop based QVCO is discussed including the transfer function and the stability. Also, this DLL architecture is implemented in a 40-nm CMOS technology. From the simulated result, this design achieves 40{\%} delay range from 6-9 GHz, with -149.1 dBc/Hz phase noise at 100 MHz frequency offset. The power consumption is 11 mW, and the phase accuracy is less than 5°.",
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Kaul, P, Gao, H, He, X & Baltus, PGM 2018, An UWB, low-noise, low-power quadrature VCO using delay-locked loop in 40-nm CMOS for image-rejection receivers. in 2018 IEEE International Symposium on Circuits and Systems, ISCAS 2018 - Proceedings., 8350984, Institute of Electrical and Electronics Engineers, Piscataway, 2018 IEEE International Symposium on Circuits and Systems, ISCAS 2018, Florence, Italy, 27/05/18. DOI: 10.1109/ISCAS.2018.8350984

An UWB, low-noise, low-power quadrature VCO using delay-locked loop in 40-nm CMOS for image-rejection receivers. / Kaul, P.; Gao, H.; He, Xin; Baltus, P.G.M.

2018 IEEE International Symposium on Circuits and Systems, ISCAS 2018 - Proceedings. Piscataway : Institute of Electrical and Electronics Engineers, 2018. 8350984.

Research output: Chapter in Book/Report/Conference proceedingConference contributionAcademicpeer-review

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N2 - This paper presents a quadrature voltage controlled oscillator (QVCO) with the delay-locked loop (DLL) for ultra wideband (UWB) application. A new architecture of delay-locked loop is presented to achieve low power consumption and low-noise operation. A system analysis of delay locked loop based QVCO is discussed including the transfer function and the stability. Also, this DLL architecture is implemented in a 40-nm CMOS technology. From the simulated result, this design achieves 40% delay range from 6-9 GHz, with -149.1 dBc/Hz phase noise at 100 MHz frequency offset. The power consumption is 11 mW, and the phase accuracy is less than 5°.

AB - This paper presents a quadrature voltage controlled oscillator (QVCO) with the delay-locked loop (DLL) for ultra wideband (UWB) application. A new architecture of delay-locked loop is presented to achieve low power consumption and low-noise operation. A system analysis of delay locked loop based QVCO is discussed including the transfer function and the stability. Also, this DLL architecture is implemented in a 40-nm CMOS technology. From the simulated result, this design achieves 40% delay range from 6-9 GHz, with -149.1 dBc/Hz phase noise at 100 MHz frequency offset. The power consumption is 11 mW, and the phase accuracy is less than 5°.

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Kaul P, Gao H, He X, Baltus PGM. An UWB, low-noise, low-power quadrature VCO using delay-locked loop in 40-nm CMOS for image-rejection receivers. In 2018 IEEE International Symposium on Circuits and Systems, ISCAS 2018 - Proceedings. Piscataway: Institute of Electrical and Electronics Engineers. 2018. 8350984. Available from, DOI: 10.1109/ISCAS.2018.8350984