An R2R-DAC-Based Architecture for Equalization-Equipped Voltage-Mode PAM-4 Wireline Transmitter Design

Boyu Hu; Yuan Du; Rulin Huang; Jeffrey Lee; Young-Kai Chen; Mau-Chung Frank Chang

doi:10.1109/TVLSI.2017.2737523

An R2R-DAC-Based Architecture for Equalization-Equipped Voltage-Mode PAM-4 Wireline Transmitter Design

Boyu Hu, Yuan Du, Rulin Huang, Jeffrey Lee, Young-Kai Chen, Mau-Chung Frank Chang

Research output: Contribution to journal › Article › Academic › peer-review

6 Citations (Scopus)

Abstract

This brief presents a wireline transmitter architecture, enabling multilevel signaling with feedforward equalization (FFE) in voltage-mode. A compact R2R-DAC-based front end is proposed and analyzed in terms of its speed, power consumption, and linearity. A voltage-mode PAM-4 transmitter with 2-tap FFE utilizing the proposed architecture is implemented in the 65-nm CMOS technology. It achieves a data rate of 34 Gb/s and an energy efficiency of 2.7 mW/Gb/s.

Original language	English
Article number	8012497
Pages (from-to)	3260-3264
Number of pages	5
Journal	IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Volume	25
Issue number	11
DOIs	https://doi.org/10.1109/TVLSI.2017.2737523
Publication status	Published - Nov 2017
Externally published	Yes

Keywords

Feed-forward equalization (FFE)
PAM-4
R2R-DAC
transmitter
voltage-mode

UN SDGs

This output contributes to the following UN Sustainable Development Goals (SDGs)

Access to Document

10.1109/TVLSI.2017.2737523

Cite this

@article{1b9d2415262e4200b63192b974222449,

title = "An R2R-DAC-Based Architecture for Equalization-Equipped Voltage-Mode PAM-4 Wireline Transmitter Design",

abstract = "This brief presents a wireline transmitter architecture, enabling multilevel signaling with feedforward equalization (FFE) in voltage-mode. A compact R2R-DAC-based front end is proposed and analyzed in terms of its speed, power consumption, and linearity. A voltage-mode PAM-4 transmitter with 2-tap FFE utilizing the proposed architecture is implemented in the 65-nm CMOS technology. It achieves a data rate of 34 Gb/s and an energy efficiency of 2.7 mW/Gb/s.",

keywords = "Feed-forward equalization (FFE), PAM-4, R2R-DAC, transmitter, voltage-mode",

author = "Boyu Hu and Yuan Du and Rulin Huang and Jeffrey Lee and Young-Kai Chen and Chang, {Mau-Chung Frank}",

note = "Publisher Copyright: {\textcopyright} 2017 IEEE.",

year = "2017",

month = nov,

doi = "10.1109/TVLSI.2017.2737523",

language = "English",

volume = "25",

pages = "3260--3264",

journal = "IEEE Transactions on Very Large Scale Integration (VLSI) Systems",

issn = "1063-8210",

publisher = "Institute of Electrical and Electronics Engineers",

number = "11",

}

TY - JOUR

T1 - An R2R-DAC-Based Architecture for Equalization-Equipped Voltage-Mode PAM-4 Wireline Transmitter Design

AU - Hu, Boyu

AU - Du, Yuan

AU - Huang, Rulin

AU - Lee, Jeffrey

AU - Chen, Young-Kai

AU - Chang, Mau-Chung Frank

PY - 2017/11

Y1 - 2017/11

N2 - This brief presents a wireline transmitter architecture, enabling multilevel signaling with feedforward equalization (FFE) in voltage-mode. A compact R2R-DAC-based front end is proposed and analyzed in terms of its speed, power consumption, and linearity. A voltage-mode PAM-4 transmitter with 2-tap FFE utilizing the proposed architecture is implemented in the 65-nm CMOS technology. It achieves a data rate of 34 Gb/s and an energy efficiency of 2.7 mW/Gb/s.

AB - This brief presents a wireline transmitter architecture, enabling multilevel signaling with feedforward equalization (FFE) in voltage-mode. A compact R2R-DAC-based front end is proposed and analyzed in terms of its speed, power consumption, and linearity. A voltage-mode PAM-4 transmitter with 2-tap FFE utilizing the proposed architecture is implemented in the 65-nm CMOS technology. It achieves a data rate of 34 Gb/s and an energy efficiency of 2.7 mW/Gb/s.

KW - Feed-forward equalization (FFE)

KW - PAM-4

KW - R2R-DAC

KW - transmitter

KW - voltage-mode

UR - http://www.scopus.com/inward/record.url?scp=85028513206&partnerID=8YFLogxK

U2 - 10.1109/TVLSI.2017.2737523

DO - 10.1109/TVLSI.2017.2737523

M3 - Article

AN - SCOPUS:85028513206

SN - 1063-8210

VL - 25

SP - 3260

EP - 3264

JO - IEEE Transactions on Very Large Scale Integration (VLSI) Systems

JF - IEEE Transactions on Very Large Scale Integration (VLSI) Systems

IS - 11

M1 - 8012497

ER -

An R2R-DAC-Based Architecture for Equalization-Equipped Voltage-Mode PAM-4 Wireline Transmitter Design

Abstract

Keywords

UN SDGs

Access to Document

Other files and links

Fingerprint

Cite this