An intra-cell defect grading tool

Alberto Bosio, Luigi Dilillo, Patrick Girard, Aida Todri-Sanial, Arnaud Virazel, S. Bernabovi, Paolo Bernardi

Research output: Chapter in Book/Report/Conference proceedingConference contributionAcademicpeer-review

5 Citations (Scopus)

Abstract

With the continuous scaling down of the transistor size, the so-called intra-cell defects are more and more frequent. In this paper we propose a defect grading tool able to evaluate the efficiency of the applied test set. The test set efficiency is quantified w.r.t. the intra-cell defect coverage and the intra-cell diagnosis resolution.
Original languageEnglish
Title of host publication17th International Symposium on Design and Diagnostics of Electronic Circuits & Systems
PublisherInstitute of Electrical and Electronics Engineers
Pages298-301
Number of pages4
ISBN (Electronic)978-1-4799-4558-0
ISBN (Print)978-1-4799-4560-3
DOIs
Publication statusPublished - 31 Jul 2014
Externally publishedYes
Event17th IEEE Symposium on Design and Diagnostics of Electronic Circuits and Systems - Warsaw, Poland
Duration: 23 Apr 201425 Apr 2014
Conference number: 17
http://ddecs2014.imio.pw.edu.pl/

Conference

Conference17th IEEE Symposium on Design and Diagnostics of Electronic Circuits and Systems
Abbreviated titleDDECS
Country/TerritoryPoland
CityWarsaw
Period23/04/1425/04/14
Internet address

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