Abstract
With the continuous scaling down of the transistor size, the so-called intra-cell defects are more and more frequent. In this paper we propose a defect grading tool able to evaluate the efficiency of the applied test set. The test set efficiency is quantified w.r.t. the intra-cell defect coverage and the intra-cell diagnosis resolution.
Original language | English |
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Title of host publication | 17th International Symposium on Design and Diagnostics of Electronic Circuits & Systems |
Publisher | Institute of Electrical and Electronics Engineers |
Pages | 298-301 |
Number of pages | 4 |
ISBN (Electronic) | 978-1-4799-4558-0 |
ISBN (Print) | 978-1-4799-4560-3 |
DOIs | |
Publication status | Published - 31 Jul 2014 |
Externally published | Yes |
Event | 17th IEEE Symposium on Design and Diagnostics of Electronic Circuits and Systems - Warsaw, Poland Duration: 23 Apr 2014 → 25 Apr 2014 Conference number: 17 http://ddecs2014.imio.pw.edu.pl/ |
Conference
Conference | 17th IEEE Symposium on Design and Diagnostics of Electronic Circuits and Systems |
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Abbreviated title | DDECS |
Country/Territory | Poland |
City | Warsaw |
Period | 23/04/14 → 25/04/14 |
Internet address |