An improved physics-based LTSpice compact electro-thermal model for a SiC power MOSFET with experimental validation

Md Maksudul Hossain; Lorenzo Ceccarelli; Arman Ur Rashid; Ramchandra M. Kotecha; H. Alan Mantooth

doi:10.1109/IECON.2018.8592522

An improved physics-based LTSpice compact electro-thermal model for a SiC power MOSFET with experimental validation

Md Maksudul Hossain, Lorenzo Ceccarelli, Arman Ur Rashid, Ramchandra M. Kotecha, H. Alan Mantooth

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › Academic › peer-review

5 Citations (Scopus)

Abstract

A compact electro-thermal SiC Power MOSFET model implemented in LTSpice is presented in this paper. A 1200 V, 90A CREE SiC power MOSFET (C2M0025120D) has been used in this work to illustrate the parameter extraction and experimental model validation. The dynamic validation has been shown using a double-pulse test circuit. The convergence has been tested with the 4-switch topology of an inverter and a comparison between MAST, Verilog-A and CREE's empirical model of the same device has also been presented.

Original language	English
Title of host publication	IECON 2018
Subtitle of host publication	44th Annual Conference of the IEEE Industrial Electronics Society
Publisher	Institute of Electrical and Electronics Engineers
Pages	1011-1016
Number of pages	6
ISBN (Electronic)	978-1-5090-6684-1
ISBN (Print)	978-1-5090-6685-8
DOIs	https://doi.org/10.1109/IECON.2018.8592522
Publication status	Published - 26 Dec 2018
Externally published	Yes
Event	44th Annual Conference of the IEEE Industrial Electronics Society (IECON 2018) - Washington, United States Duration: 21 Oct 2018 → 23 Oct 2018 Conference number: 44 http://www.iecon2018.org/

Conference

Conference	44th Annual Conference of the IEEE Industrial Electronics Society (IECON 2018)
Abbreviated title	IECON
Country/Territory	United States
City	Washington
Period	21/10/18 → 23/10/18
Internet address	http://www.iecon2018.org/

Keywords

Compact model
Electro-thermal model
LTSpice
Saber
SiC MOSFET

Access to Document

10.1109/IECON.2018.8592522

Cite this

Hossain, M. M., Ceccarelli, L., Rashid, A. U., Kotecha, R. M., & Alan Mantooth, H. (2018). An improved physics-based LTSpice compact electro-thermal model for a SiC power MOSFET with experimental validation. In IECON 2018: 44th Annual Conference of the IEEE Industrial Electronics Society (pp. 1011-1016). [8592522] Institute of Electrical and Electronics Engineers. https://doi.org/10.1109/IECON.2018.8592522

Hossain, Md Maksudul ; Ceccarelli, Lorenzo ; Rashid, Arman Ur ; Kotecha, Ramchandra M. ; Alan Mantooth, H. / An improved physics-based LTSpice compact electro-thermal model for a SiC power MOSFET with experimental validation. IECON 2018: 44th Annual Conference of the IEEE Industrial Electronics Society. Institute of Electrical and Electronics Engineers, 2018. pp. 1011-1016

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title = "An improved physics-based LTSpice compact electro-thermal model for a SiC power MOSFET with experimental validation",

abstract = "A compact electro-thermal SiC Power MOSFET model implemented in LTSpice is presented in this paper. A 1200 V, 90A CREE SiC power MOSFET (C2M0025120D) has been used in this work to illustrate the parameter extraction and experimental model validation. The dynamic validation has been shown using a double-pulse test circuit. The convergence has been tested with the 4-switch topology of an inverter and a comparison between MAST, Verilog-A and CREE's empirical model of the same device has also been presented.",

keywords = "Compact model, Electro-thermal model, LTSpice, Saber, SiC MOSFET",

author = "Hossain, {Md Maksudul} and Lorenzo Ceccarelli and Rashid, {Arman Ur} and Kotecha, {Ramchandra M.} and {Alan Mantooth}, H.",

note = "Publisher Copyright: {\textcopyright} 2018 IEEE.; 44th Annual Conference of the IEEE Industrial Electronics Society (IECON 2018), IECON ; Conference date: 21-10-2018 Through 23-10-2018",

year = "2018",

month = dec,

day = "26",

doi = "10.1109/IECON.2018.8592522",

language = "English",

isbn = "978-1-5090-6685-8",

pages = "1011--1016",

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publisher = "Institute of Electrical and Electronics Engineers",

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Hossain, MM, Ceccarelli, L, Rashid, AU, Kotecha, RM & Alan Mantooth, H 2018, An improved physics-based LTSpice compact electro-thermal model for a SiC power MOSFET with experimental validation. in IECON 2018: 44th Annual Conference of the IEEE Industrial Electronics Society., 8592522, Institute of Electrical and Electronics Engineers, pp. 1011-1016, 44th Annual Conference of the IEEE Industrial Electronics Society (IECON 2018), Washington, United States, 21/10/18. https://doi.org/10.1109/IECON.2018.8592522

An improved physics-based LTSpice compact electro-thermal model for a SiC power MOSFET with experimental validation. / Hossain, Md Maksudul; Ceccarelli, Lorenzo; Rashid, Arman Ur; Kotecha, Ramchandra M.; Alan Mantooth, H.

IECON 2018: 44th Annual Conference of the IEEE Industrial Electronics Society. Institute of Electrical and Electronics Engineers, 2018. p. 1011-1016 8592522.

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › Academic › peer-review

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AU - Hossain, Md Maksudul

AU - Ceccarelli, Lorenzo

AU - Rashid, Arman Ur

AU - Kotecha, Ramchandra M.

AU - Alan Mantooth, H.

N1 - Conference code: 44

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Y1 - 2018/12/26

N2 - A compact electro-thermal SiC Power MOSFET model implemented in LTSpice is presented in this paper. A 1200 V, 90A CREE SiC power MOSFET (C2M0025120D) has been used in this work to illustrate the parameter extraction and experimental model validation. The dynamic validation has been shown using a double-pulse test circuit. The convergence has been tested with the 4-switch topology of an inverter and a comparison between MAST, Verilog-A and CREE's empirical model of the same device has also been presented.

AB - A compact electro-thermal SiC Power MOSFET model implemented in LTSpice is presented in this paper. A 1200 V, 90A CREE SiC power MOSFET (C2M0025120D) has been used in this work to illustrate the parameter extraction and experimental model validation. The dynamic validation has been shown using a double-pulse test circuit. The convergence has been tested with the 4-switch topology of an inverter and a comparison between MAST, Verilog-A and CREE's empirical model of the same device has also been presented.

KW - Compact model

KW - Electro-thermal model

KW - LTSpice

KW - Saber

KW - SiC MOSFET

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DO - 10.1109/IECON.2018.8592522

M3 - Conference contribution

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SN - 978-1-5090-6685-8

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BT - IECON 2018

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Hossain MM, Ceccarelli L, Rashid AU, Kotecha RM, Alan Mantooth H. An improved physics-based LTSpice compact electro-thermal model for a SiC power MOSFET with experimental validation. In IECON 2018: 44th Annual Conference of the IEEE Industrial Electronics Society. Institute of Electrical and Electronics Engineers. 2018. p. 1011-1016. 8592522 https://doi.org/10.1109/IECON.2018.8592522

An improved physics-based LTSpice compact electro-thermal model for a SiC power MOSFET with experimental validation

Abstract

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Keywords

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