An improved algorithm for slot selection in the AEthereal network-on-chip

R.A. Stefan; K.G.W. Goossens

doi:10.1145/1930037.1930040

An improved algorithm for slot selection in the AEthereal network-on-chip

R.A. Stefan, K.G.W. Goossens

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › Academic › peer-review

4 Citations (Scopus)

Abstract

The rapid development in the electronics industry leads to a design process dominated by time-to-market constraints. The balance is shifted from logic design to packaging of already existing IP which results in a search for solutions for interconnecting the IP blocks. Networks-on-chip allow the rapid development a scalable interconnect and with the use of Circuit switching they can also provide guarantees for the speed of communication between IPs. In the current paper we demonstrate an improvement in the allocation algorithms for a Time-Division-Multiplexing Circuit-Switching scheme. We prove our algorithm to be optimal and we find that it provides an improvement of up to 26.7% compared to the previously proposed algorithm. The gain is more attractive as it comes at no cost for the actual hardware implementation.

Original language	English
Title of host publication	Proceedings of the 6th International Workshop on Interconnection Network Architecture: On-Chip, Multi-Chip (INA-OCMC 2011), 23 January 2011, Heraklion, Greece
Publisher	Association for Computing Machinery, Inc
Pages	7-10
ISBN (Print)	978-1-4503-0272-2
DOIs	https://doi.org/10.1145/1930037.1930040
Publication status	Published - 2011
Event	conference; INA-OMC 2011; 2011-01-23; 2011-01-23 - Duration: 23 Jan 2011 → 23 Jan 2011

Conference

Conference	conference; INA-OMC 2011; 2011-01-23; 2011-01-23
Period	23/01/11 → 23/01/11
Other	INA-OMC 2011

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Stefan, R. A., & Goossens, K. G. W. (2011). An improved algorithm for slot selection in the AEthereal network-on-chip. In Proceedings of the 6th International Workshop on Interconnection Network Architecture: On-Chip, Multi-Chip (INA-OCMC 2011), 23 January 2011, Heraklion, Greece (pp. 7-10). Association for Computing Machinery, Inc. https://doi.org/10.1145/1930037.1930040

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title = "An improved algorithm for slot selection in the AEthereal network-on-chip",

abstract = "The rapid development in the electronics industry leads to a design process dominated by time-to-market constraints. The balance is shifted from logic design to packaging of already existing IP which results in a search for solutions for interconnecting the IP blocks. Networks-on-chip allow the rapid development a scalable interconnect and with the use of Circuit switching they can also provide guarantees for the speed of communication between IPs. In the current paper we demonstrate an improvement in the allocation algorithms for a Time-Division-Multiplexing Circuit-Switching scheme. We prove our algorithm to be optimal and we find that it provides an improvement of up to 26.7% compared to the previously proposed algorithm. The gain is more attractive as it comes at no cost for the actual hardware implementation.",

author = "R.A. Stefan and K.G.W. Goossens",

year = "2011",

doi = "10.1145/1930037.1930040",

language = "English",

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publisher = "Association for Computing Machinery, Inc",

address = "United States",

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Stefan, RA & Goossens, KGW 2011, An improved algorithm for slot selection in the AEthereal network-on-chip. in Proceedings of the 6th International Workshop on Interconnection Network Architecture: On-Chip, Multi-Chip (INA-OCMC 2011), 23 January 2011, Heraklion, Greece. Association for Computing Machinery, Inc, pp. 7-10, conference; INA-OMC 2011; 2011-01-23; 2011-01-23, 23/01/11. https://doi.org/10.1145/1930037.1930040

An improved algorithm for slot selection in the AEthereal network-on-chip. / Stefan, R.A.; Goossens, K.G.W.
Proceedings of the 6th International Workshop on Interconnection Network Architecture: On-Chip, Multi-Chip (INA-OCMC 2011), 23 January 2011, Heraklion, Greece. Association for Computing Machinery, Inc, 2011. p. 7-10.

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › Academic › peer-review

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AU - Goossens, K.G.W.

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N2 - The rapid development in the electronics industry leads to a design process dominated by time-to-market constraints. The balance is shifted from logic design to packaging of already existing IP which results in a search for solutions for interconnecting the IP blocks. Networks-on-chip allow the rapid development a scalable interconnect and with the use of Circuit switching they can also provide guarantees for the speed of communication between IPs. In the current paper we demonstrate an improvement in the allocation algorithms for a Time-Division-Multiplexing Circuit-Switching scheme. We prove our algorithm to be optimal and we find that it provides an improvement of up to 26.7% compared to the previously proposed algorithm. The gain is more attractive as it comes at no cost for the actual hardware implementation.

AB - The rapid development in the electronics industry leads to a design process dominated by time-to-market constraints. The balance is shifted from logic design to packaging of already existing IP which results in a search for solutions for interconnecting the IP blocks. Networks-on-chip allow the rapid development a scalable interconnect and with the use of Circuit switching they can also provide guarantees for the speed of communication between IPs. In the current paper we demonstrate an improvement in the allocation algorithms for a Time-Division-Multiplexing Circuit-Switching scheme. We prove our algorithm to be optimal and we find that it provides an improvement of up to 26.7% compared to the previously proposed algorithm. The gain is more attractive as it comes at no cost for the actual hardware implementation.

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DO - 10.1145/1930037.1930040

M3 - Conference contribution

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BT - Proceedings of the 6th International Workshop on Interconnection Network Architecture: On-Chip, Multi-Chip (INA-OCMC 2011), 23 January 2011, Heraklion, Greece

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Y2 - 23 January 2011 through 23 January 2011

ER -

An improved algorithm for slot selection in the AEthereal network-on-chip

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