An improved algorithm for slot selection in the AEthereal network-on-chip

R.A. Stefan, K.G.W. Goossens

Research output: Chapter in Book/Report/Conference proceedingConference contributionAcademicpeer-review

4 Citations (Scopus)


The rapid development in the electronics industry leads to a design process dominated by time-to-market constraints. The balance is shifted from logic design to packaging of already existing IP which results in a search for solutions for interconnecting the IP blocks. Networks-on-chip allow the rapid development a scalable interconnect and with the use of Circuit switching they can also provide guarantees for the speed of communication between IPs. In the current paper we demonstrate an improvement in the allocation algorithms for a Time-Division-Multiplexing Circuit-Switching scheme. We prove our algorithm to be optimal and we find that it provides an improvement of up to 26.7% compared to the previously proposed algorithm. The gain is more attractive as it comes at no cost for the actual hardware implementation.
Original languageEnglish
Title of host publicationProceedings of the 6th International Workshop on Interconnection Network Architecture: On-Chip, Multi-Chip (INA-OCMC 2011), 23 January 2011, Heraklion, Greece
PublisherAssociation for Computing Machinery, Inc
ISBN (Print)978-1-4503-0272-2
Publication statusPublished - 2011
Eventconference; INA-OMC 2011; 2011-01-23; 2011-01-23 -
Duration: 23 Jan 201123 Jan 2011


Conferenceconference; INA-OMC 2011; 2011-01-23; 2011-01-23
OtherINA-OMC 2011


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