An HEVC fractional interpolation hardware using memory based constant multiplication

Ahmet Can Mert; Ercan Kalali; Ilker Hamzaoglu

doi:10.1109/ICCE.2018.8326312

An HEVC fractional interpolation hardware using memory based constant multiplication

Ahmet Can Mert, Ercan Kalali, Ilker Hamzaoglu

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › Academic › peer-review

4 Citations (Scopus)

Abstract

Fractional interpolation is one of the most computationally intensive parts of High Efficiency Video Coding (HEVC) video encoder and decoder. In this paper, an HEVC fractional interpolation hardware using memory based constant multiplication is proposed. The proposed hardware uses memory based constant multiplication technique for implementing multiplication with constant coefficients. The proposed memory based constant multiplication hardware stores pre-computed products of an input pixel with multiple constant coefficients in memory. Several optimizations are proposed to reduce memory size. The proposed HEVC fractional interpolation hardware, in the worst case, can process 35 quad full HD (3840×2160) video frames per second. It has up to 31% less energy consumption than original HEVC fractional interpolation hardware.

Original language	English
Title of host publication	2018 IEEE International Conference on Consumer Electronics (ICCE)
Editors	Saraju P. Mohanty, Peter Corcoran, Hai Li, Anirban Sengupta, Jong-Hyouk Lee
Publisher	Institute of Electrical and Electronics Engineers
Pages	1-5
Number of pages	5
ISBN (Electronic)	978-1-5386-3025-9
DOIs	https://doi.org/10.1109/ICCE.2018.8326312
Publication status	Published - 29 Mar 2018
Externally published	Yes
Event	2018 IEEE International Conference on Consumer Electronics, ICCE 2018 - Las Vegas, United States Duration: 12 Jan 2018 → 14 Jan 2018 Conference number: 36

Conference

Conference	2018 IEEE International Conference on Consumer Electronics, ICCE 2018
Abbreviated title	ICCE 2018
Country/Territory	United States
City	Las Vegas
Period	12/01/18 → 14/01/18

Keywords

Fractional Interpolation
Hardware Implementation
HEVC
Memory Based Multiplication

UN SDGs

This output contributes to the following UN Sustainable Development Goals (SDGs)

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10.1109/ICCE.2018.8326312

Cite this

Mert, A. C., Kalali, E., & Hamzaoglu, I. (2018). An HEVC fractional interpolation hardware using memory based constant multiplication. In S. P. Mohanty, P. Corcoran, H. Li, A. Sengupta, & J.-H. Lee (Eds.), 2018 IEEE International Conference on Consumer Electronics (ICCE) (pp. 1-5). Article 8326312 Institute of Electrical and Electronics Engineers. https://doi.org/10.1109/ICCE.2018.8326312

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title = "An HEVC fractional interpolation hardware using memory based constant multiplication",

abstract = "Fractional interpolation is one of the most computationally intensive parts of High Efficiency Video Coding (HEVC) video encoder and decoder. In this paper, an HEVC fractional interpolation hardware using memory based constant multiplication is proposed. The proposed hardware uses memory based constant multiplication technique for implementing multiplication with constant coefficients. The proposed memory based constant multiplication hardware stores pre-computed products of an input pixel with multiple constant coefficients in memory. Several optimizations are proposed to reduce memory size. The proposed HEVC fractional interpolation hardware, in the worst case, can process 35 quad full HD (3840×2160) video frames per second. It has up to 31% less energy consumption than original HEVC fractional interpolation hardware.",

keywords = "Fractional Interpolation, Hardware Implementation, HEVC, Memory Based Multiplication",

author = "Mert, {Ahmet Can} and Ercan Kalali and Ilker Hamzaoglu",

note = "Publisher Copyright: {\textcopyright} 2018 IEEE.; 2018 IEEE International Conference on Consumer Electronics, ICCE 2018, ICCE 2018 ; Conference date: 12-01-2018 Through 14-01-2018",

year = "2018",

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doi = "10.1109/ICCE.2018.8326312",

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editor = "Mohanty, {Saraju P.} and Peter Corcoran and Hai Li and Anirban Sengupta and Jong-Hyouk Lee",

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Mert, AC, Kalali, E & Hamzaoglu, I 2018, An HEVC fractional interpolation hardware using memory based constant multiplication. in SP Mohanty, P Corcoran, H Li, A Sengupta & J-H Lee (eds), 2018 IEEE International Conference on Consumer Electronics (ICCE)., 8326312, Institute of Electrical and Electronics Engineers, pp. 1-5, 2018 IEEE International Conference on Consumer Electronics, ICCE 2018, Las Vegas, Nevada, United States, 12/01/18. https://doi.org/10.1109/ICCE.2018.8326312

An HEVC fractional interpolation hardware using memory based constant multiplication. / Mert, Ahmet Can; Kalali, Ercan; Hamzaoglu, Ilker.
2018 IEEE International Conference on Consumer Electronics (ICCE). ed. / Saraju P. Mohanty; Peter Corcoran; Hai Li; Anirban Sengupta; Jong-Hyouk Lee. Institute of Electrical and Electronics Engineers, 2018. p. 1-5 8326312.

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › Academic › peer-review

TY - GEN

T1 - An HEVC fractional interpolation hardware using memory based constant multiplication

AU - Mert, Ahmet Can

AU - Kalali, Ercan

AU - Hamzaoglu, Ilker

N1 - Conference code: 36

PY - 2018/3/29

Y1 - 2018/3/29

N2 - Fractional interpolation is one of the most computationally intensive parts of High Efficiency Video Coding (HEVC) video encoder and decoder. In this paper, an HEVC fractional interpolation hardware using memory based constant multiplication is proposed. The proposed hardware uses memory based constant multiplication technique for implementing multiplication with constant coefficients. The proposed memory based constant multiplication hardware stores pre-computed products of an input pixel with multiple constant coefficients in memory. Several optimizations are proposed to reduce memory size. The proposed HEVC fractional interpolation hardware, in the worst case, can process 35 quad full HD (3840×2160) video frames per second. It has up to 31% less energy consumption than original HEVC fractional interpolation hardware.

AB - Fractional interpolation is one of the most computationally intensive parts of High Efficiency Video Coding (HEVC) video encoder and decoder. In this paper, an HEVC fractional interpolation hardware using memory based constant multiplication is proposed. The proposed hardware uses memory based constant multiplication technique for implementing multiplication with constant coefficients. The proposed memory based constant multiplication hardware stores pre-computed products of an input pixel with multiple constant coefficients in memory. Several optimizations are proposed to reduce memory size. The proposed HEVC fractional interpolation hardware, in the worst case, can process 35 quad full HD (3840×2160) video frames per second. It has up to 31% less energy consumption than original HEVC fractional interpolation hardware.

KW - Fractional Interpolation

KW - Hardware Implementation

KW - HEVC

KW - Memory Based Multiplication

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U2 - 10.1109/ICCE.2018.8326312

DO - 10.1109/ICCE.2018.8326312

M3 - Conference contribution

SP - 1

EP - 5

BT - 2018 IEEE International Conference on Consumer Electronics (ICCE)

A2 - Mohanty, Saraju P.

A2 - Corcoran, Peter

A2 - Li, Hai

A2 - Sengupta, Anirban

A2 - Lee, Jong-Hyouk

PB - Institute of Electrical and Electronics Engineers

T2 - 2018 IEEE International Conference on Consumer Electronics, ICCE 2018

Y2 - 12 January 2018 through 14 January 2018

ER -

An HEVC fractional interpolation hardware using memory based constant multiplication

Abstract

Conference

Keywords

UN SDGs

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