Abstract
Future Video Coding (FVC) is a new international video compression standard offering much better compression efficiency than previous video compression standards at the expense of much higher computational complexity. In this paper, an FPGA implementation of FVC 2D transform is proposed. The proposed FVC 2D transform hardware can perform 2D DCT-II, DCT-V, DCT-VIII, DST-I, DST-VII operations for 4×4 and 8×8 transform units. It uses two reconfigurable datapaths for all 1D transforms. It implements multiplications with constants using DSP blocks in FPGA. The proposed FPGA implementation, in the worst case, can process 54 8K Ultra HD (7680×4320) video frames per second. The proposed FPGA implementation has up to 29% less energy consumption than the FPGA implementation of FVC 2D transform hardware in the literature.
Original language | English |
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Title of host publication | 2017 IEEE 7th International Conference on Consumer Electronics - Berlin (ICCE-Berlin) |
Publisher | Institute of Electrical and Electronics Engineers |
Pages | 31-36 |
Number of pages | 6 |
ISBN (Electronic) | 978-1-5090-4014-8 |
DOIs | |
Publication status | Published - 18 Dec 2017 |
Externally published | Yes |
Event | 7th IEEE International Conference on Consumer Electronics - Berlin, ICCE-Berlin 2017 - Berlin, Germany Duration: 3 Sept 2017 → 6 Sept 2017 |
Conference
Conference | 7th IEEE International Conference on Consumer Electronics - Berlin, ICCE-Berlin 2017 |
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Country/Territory | Germany |
City | Berlin |
Period | 3/09/17 → 6/09/17 |
Keywords
- Discrete Cosine Transform
- Discrete Sine Transform
- FPGA
- FVC
- Hardware Implementation