An FPGA implementation of future video coding 2D transform

Ahmet Can Mert; Ercan Kalali; Ilker Hamzaoglu

doi:10.1109/ICCE-Berlin.2017.8210582

An FPGA implementation of future video coding 2D transform

Ahmet Can Mert, Ercan Kalali, Ilker Hamzaoglu

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › Academic › peer-review

13 Citations (Scopus)

Abstract

Future Video Coding (FVC) is a new international video compression standard offering much better compression efficiency than previous video compression standards at the expense of much higher computational complexity. In this paper, an FPGA implementation of FVC 2D transform is proposed. The proposed FVC 2D transform hardware can perform 2D DCT-II, DCT-V, DCT-VIII, DST-I, DST-VII operations for 4×4 and 8×8 transform units. It uses two reconfigurable datapaths for all 1D transforms. It implements multiplications with constants using DSP blocks in FPGA. The proposed FPGA implementation, in the worst case, can process 54 8K Ultra HD (7680×4320) video frames per second. The proposed FPGA implementation has up to 29% less energy consumption than the FPGA implementation of FVC 2D transform hardware in the literature.

Original language	English
Title of host publication	2017 IEEE 7th International Conference on Consumer Electronics - Berlin (ICCE-Berlin)
Publisher	Institute of Electrical and Electronics Engineers
Pages	31-36
Number of pages	6
ISBN (Electronic)	978-1-5090-4014-8
DOIs	https://doi.org/10.1109/ICCE-Berlin.2017.8210582
Publication status	Published - 18 Dec 2017
Externally published	Yes
Event	7th IEEE International Conference on Consumer Electronics - Berlin, ICCE-Berlin 2017 - Berlin, Germany Duration: 3 Sept 2017 → 6 Sept 2017

Conference

Conference	7th IEEE International Conference on Consumer Electronics - Berlin, ICCE-Berlin 2017
Country/Territory	Germany
City	Berlin
Period	3/09/17 → 6/09/17

Keywords

Discrete Cosine Transform
Discrete Sine Transform
FPGA
FVC
Hardware Implementation

UN SDGs

This output contributes to the following UN Sustainable Development Goals (SDGs)

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10.1109/ICCE-Berlin.2017.8210582

Cite this

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title = "An FPGA implementation of future video coding 2D transform",

abstract = "Future Video Coding (FVC) is a new international video compression standard offering much better compression efficiency than previous video compression standards at the expense of much higher computational complexity. In this paper, an FPGA implementation of FVC 2D transform is proposed. The proposed FVC 2D transform hardware can perform 2D DCT-II, DCT-V, DCT-VIII, DST-I, DST-VII operations for 4×4 and 8×8 transform units. It uses two reconfigurable datapaths for all 1D transforms. It implements multiplications with constants using DSP blocks in FPGA. The proposed FPGA implementation, in the worst case, can process 54 8K Ultra HD (7680×4320) video frames per second. The proposed FPGA implementation has up to 29% less energy consumption than the FPGA implementation of FVC 2D transform hardware in the literature.",

keywords = "Discrete Cosine Transform, Discrete Sine Transform, FPGA, FVC, Hardware Implementation",

author = "Mert, {Ahmet Can} and Ercan Kalali and Ilker Hamzaoglu",

note = "Publisher Copyright: {\textcopyright} 2017 IEEE.; 7th IEEE International Conference on Consumer Electronics - Berlin, ICCE-Berlin 2017 ; Conference date: 03-09-2017 Through 06-09-2017",

year = "2017",

month = dec,

day = "18",

doi = "10.1109/ICCE-Berlin.2017.8210582",

language = "English",

pages = "31--36",

booktitle = "2017 IEEE 7th International Conference on Consumer Electronics - Berlin (ICCE-Berlin)",

publisher = "Institute of Electrical and Electronics Engineers",

address = "United States",

}

Mert, AC, Kalali, E & Hamzaoglu, I 2017, An FPGA implementation of future video coding 2D transform. in 2017 IEEE 7th International Conference on Consumer Electronics - Berlin (ICCE-Berlin)., 8210582, Institute of Electrical and Electronics Engineers, pp. 31-36, 7th IEEE International Conference on Consumer Electronics - Berlin, ICCE-Berlin 2017, Berlin, Germany, 3/09/17. https://doi.org/10.1109/ICCE-Berlin.2017.8210582

An FPGA implementation of future video coding 2D transform. / Mert, Ahmet Can; Kalali, Ercan; Hamzaoglu, Ilker.
2017 IEEE 7th International Conference on Consumer Electronics - Berlin (ICCE-Berlin). Institute of Electrical and Electronics Engineers, 2017. p. 31-36 8210582.

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › Academic › peer-review

TY - GEN

T1 - An FPGA implementation of future video coding 2D transform

AU - Mert, Ahmet Can

AU - Kalali, Ercan

AU - Hamzaoglu, Ilker

PY - 2017/12/18

Y1 - 2017/12/18

N2 - Future Video Coding (FVC) is a new international video compression standard offering much better compression efficiency than previous video compression standards at the expense of much higher computational complexity. In this paper, an FPGA implementation of FVC 2D transform is proposed. The proposed FVC 2D transform hardware can perform 2D DCT-II, DCT-V, DCT-VIII, DST-I, DST-VII operations for 4×4 and 8×8 transform units. It uses two reconfigurable datapaths for all 1D transforms. It implements multiplications with constants using DSP blocks in FPGA. The proposed FPGA implementation, in the worst case, can process 54 8K Ultra HD (7680×4320) video frames per second. The proposed FPGA implementation has up to 29% less energy consumption than the FPGA implementation of FVC 2D transform hardware in the literature.

AB - Future Video Coding (FVC) is a new international video compression standard offering much better compression efficiency than previous video compression standards at the expense of much higher computational complexity. In this paper, an FPGA implementation of FVC 2D transform is proposed. The proposed FVC 2D transform hardware can perform 2D DCT-II, DCT-V, DCT-VIII, DST-I, DST-VII operations for 4×4 and 8×8 transform units. It uses two reconfigurable datapaths for all 1D transforms. It implements multiplications with constants using DSP blocks in FPGA. The proposed FPGA implementation, in the worst case, can process 54 8K Ultra HD (7680×4320) video frames per second. The proposed FPGA implementation has up to 29% less energy consumption than the FPGA implementation of FVC 2D transform hardware in the literature.

KW - Discrete Cosine Transform

KW - Discrete Sine Transform

KW - FPGA

KW - FVC

KW - Hardware Implementation

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U2 - 10.1109/ICCE-Berlin.2017.8210582

DO - 10.1109/ICCE-Berlin.2017.8210582

M3 - Conference contribution

SP - 31

EP - 36

BT - 2017 IEEE 7th International Conference on Consumer Electronics - Berlin (ICCE-Berlin)

PB - Institute of Electrical and Electronics Engineers

T2 - 7th IEEE International Conference on Consumer Electronics - Berlin, ICCE-Berlin 2017

Y2 - 3 September 2017 through 6 September 2017

ER -

An FPGA implementation of future video coding 2D transform

Abstract

Conference

Keywords

UN SDGs

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