An FPGA bridge preserving traffic quality of service for on-chip network-based systems

Ashkan Beyranvand Nejad; Matias Escudero Martinez; Kees Goossens

doi:10.1109/DATE.2011.5763074

An FPGA bridge preserving traffic quality of service for on-chip network-based systems

Ashkan Beyranvand Nejad, Matias Escudero Martinez, Kees Goossens

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › Academic › peer-review

7 Citations (Scopus)

Abstract

FPGA prototyping of recent large Systems on Chip (SoCs) is very challenging due to the resource limitation of a single FPGA. Moreover, having external access to SoCs for verification and debug purposes is essential. In this paper, we suggest to partition a network-on-chip (NoC) based system into smaller sub-systems each with their own NoC, and each of which is implemented on a separate FPGA board. Multiple SoC ASICs can be bridged in the same way. The scheme that interconnects the sub-systems should offer the application connections the required quality of service (QoS). In this paper, we investigate bridging schemes at different levels of the NoC protocol stack. Comparing the distinct design criteria for the proposed schemes, a bridge is designed. The bridge experiments show that it provides QoS in terms of bandwith and latency.

Original language	English
Title of host publication	Proceedings - Design, Automation and Test in Europe Conference and Exhibition, DATE 2011
Place of Publication	Piscataway
Publisher	Institute of Electrical and Electronics Engineers
Pages	425-430
Number of pages	6
ISBN (Electronic)	978-3-9810801-8-6
ISBN (Print)	978-1-61284-208-0
DOIs	https://doi.org/10.1109/DATE.2011.5763074
Publication status	Published - 31 May 2011
Event	14th Design, Automation and Test in Europe Conference and Exhibition (DATE 2011) - Alpexpo Espace Alpes Congres, Grenoble, France Duration: 14 Mar 2011 → 18 Mar 2011 Conference number: 14 https://www.date-conference.com/date11/

Conference

Conference	14th Design, Automation and Test in Europe Conference and Exhibition (DATE 2011)
Abbreviated title	DATE 2011
Country/Territory	France
City	Grenoble
Period	14/03/11 → 18/03/11
Internet address	https://www.date-conference.com/date11/

Access to Document

10.1109/DATE.2011.5763074

Cite this

@inproceedings{4a2b8af043a14fa792177460288e00ae,

title = "An FPGA bridge preserving traffic quality of service for on-chip network-based systems",

abstract = "FPGA prototyping of recent large Systems on Chip (SoCs) is very challenging due to the resource limitation of a single FPGA. Moreover, having external access to SoCs for verification and debug purposes is essential. In this paper, we suggest to partition a network-on-chip (NoC) based system into smaller sub-systems each with their own NoC, and each of which is implemented on a separate FPGA board. Multiple SoC ASICs can be bridged in the same way. The scheme that interconnects the sub-systems should offer the application connections the required quality of service (QoS). In this paper, we investigate bridging schemes at different levels of the NoC protocol stack. Comparing the distinct design criteria for the proposed schemes, a bridge is designed. The bridge experiments show that it provides QoS in terms of bandwith and latency.",

author = "Nejad, {Ashkan Beyranvand} and Martinez, {Matias Escudero} and Kees Goossens",

year = "2011",

month = may,

day = "31",

doi = "10.1109/DATE.2011.5763074",

language = "English",

isbn = "978-1-61284-208-0",

pages = "425--430",

booktitle = "Proceedings - Design, Automation and Test in Europe Conference and Exhibition, DATE 2011",

publisher = "Institute of Electrical and Electronics Engineers",

address = "United States",

note = "14th Design, Automation and Test in Europe Conference and Exhibition (DATE 2011) , DATE 2011 ; Conference date: 14-03-2011 Through 18-03-2011",

url = "https://www.date-conference.com/date11/",

}

Nejad, AB, Martinez, ME & Goossens, K 2011, An FPGA bridge preserving traffic quality of service for on-chip network-based systems. in Proceedings - Design, Automation and Test in Europe Conference and Exhibition, DATE 2011., 5763074, Institute of Electrical and Electronics Engineers, Piscataway, pp. 425-430, 14th Design, Automation and Test in Europe Conference and Exhibition (DATE 2011)
, Grenoble, France, 14/03/11. https://doi.org/10.1109/DATE.2011.5763074

An FPGA bridge preserving traffic quality of service for on-chip network-based systems. / Nejad, Ashkan Beyranvand; Martinez, Matias Escudero; Goossens, Kees.
Proceedings - Design, Automation and Test in Europe Conference and Exhibition, DATE 2011. Piscataway: Institute of Electrical and Electronics Engineers, 2011. p. 425-430 5763074.

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › Academic › peer-review

TY - GEN

T1 - An FPGA bridge preserving traffic quality of service for on-chip network-based systems

AU - Nejad, Ashkan Beyranvand

AU - Martinez, Matias Escudero

AU - Goossens, Kees

N1 - Conference code: 14

PY - 2011/5/31

Y1 - 2011/5/31

N2 - FPGA prototyping of recent large Systems on Chip (SoCs) is very challenging due to the resource limitation of a single FPGA. Moreover, having external access to SoCs for verification and debug purposes is essential. In this paper, we suggest to partition a network-on-chip (NoC) based system into smaller sub-systems each with their own NoC, and each of which is implemented on a separate FPGA board. Multiple SoC ASICs can be bridged in the same way. The scheme that interconnects the sub-systems should offer the application connections the required quality of service (QoS). In this paper, we investigate bridging schemes at different levels of the NoC protocol stack. Comparing the distinct design criteria for the proposed schemes, a bridge is designed. The bridge experiments show that it provides QoS in terms of bandwith and latency.

AB - FPGA prototyping of recent large Systems on Chip (SoCs) is very challenging due to the resource limitation of a single FPGA. Moreover, having external access to SoCs for verification and debug purposes is essential. In this paper, we suggest to partition a network-on-chip (NoC) based system into smaller sub-systems each with their own NoC, and each of which is implemented on a separate FPGA board. Multiple SoC ASICs can be bridged in the same way. The scheme that interconnects the sub-systems should offer the application connections the required quality of service (QoS). In this paper, we investigate bridging schemes at different levels of the NoC protocol stack. Comparing the distinct design criteria for the proposed schemes, a bridge is designed. The bridge experiments show that it provides QoS in terms of bandwith and latency.

UR - http://www.scopus.com/inward/record.url?scp=79957573681&partnerID=8YFLogxK

U2 - 10.1109/DATE.2011.5763074

DO - 10.1109/DATE.2011.5763074

M3 - Conference contribution

AN - SCOPUS:79957573681

SN - 978-1-61284-208-0

SP - 425

EP - 430

BT - Proceedings - Design, Automation and Test in Europe Conference and Exhibition, DATE 2011

PB - Institute of Electrical and Electronics Engineers

CY - Piscataway

T2 - 14th Design, Automation and Test in Europe Conference and Exhibition (DATE 2011)

Y2 - 14 March 2011 through 18 March 2011

ER -

An FPGA bridge preserving traffic quality of service for on-chip network-based systems

Abstract

Conference

Access to Document

Other files and links

Fingerprint

Cite this