An exercise in the automatic verification of asynchronous designs

A.M. Bailey, G.A. McCaskill, G.J. Milne

Research output: Contribution to journalArticleAcademicpeer-review

13 Citations (Scopus)


This paper illustrates the practical application of an automatic formal verification technique to circuit designs of realistic complexity. The Circal System is presented and a number of asynchronous hardware modules are described and formally verified using it. Asynchronous logic is generally considered hard to design and analyse, and this serves as an appropriate demonstration of the features of a formal description and verification system.
Original languageEnglish
Pages (from-to)213-242
JournalFormal Methods in System Design
Issue number3
Publication statusPublished - 1994


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