TY - GEN
T1 - An Event-Driven Recurrent Spiking Neural Network Architecture for Efficient Inference on FPGA
AU - Sankaran, Anand
AU - Detterer, Paul
AU - Kannan, Kalpana
AU - Alachiotis, Nikolaos
AU - Corradi, Federico
PY - 2022/7/27
Y1 - 2022/7/27
N2 - Spiking Neural Network (SNN) architectures are promising candidates for executing machine intelligence at the edge while meeting strict energy and cost reduction constraints in several application areas. To this end, we propose a new digital architecture compatible with Recurrent Spiking Neural Networks (RSNNs) trained using the PyTorch framework and Back-Propagation-Through-Time (BPTT) for optimizing the weights and the neuron’s parameters. Our architecture offers high software-to-hardware fidelity, providing high accuracy and a low number of spikes, and it targets efficient and low-cost implementations in Field Programmable Gate Arrays (FPGAs). We introduce a new time-discretization technique that uses request-acknowledge cycles between layers to allow the layer’s time execution to depend only upon the number of spikes. As a result, we achieve between 1.7x and 30x lower resource utilization and between 11x and 61x fewer spikes per inference than previous SNN implementations in FPGAs that rely on on-chip memory to store spike-time information and weight values. We demonstrate our approach using two benchmarks: MNIST digit recognition and a realistic radar and image sensory fusion for cropland classifications. Our results demonstrate that we can exploit the trade-off between accuracy, latency, and resource utilization at design time. Moreover, the use of low-cost FPGA platforms enables the deployment of several applications by satisfying the strict constraints of edge machine learning devices.
AB - Spiking Neural Network (SNN) architectures are promising candidates for executing machine intelligence at the edge while meeting strict energy and cost reduction constraints in several application areas. To this end, we propose a new digital architecture compatible with Recurrent Spiking Neural Networks (RSNNs) trained using the PyTorch framework and Back-Propagation-Through-Time (BPTT) for optimizing the weights and the neuron’s parameters. Our architecture offers high software-to-hardware fidelity, providing high accuracy and a low number of spikes, and it targets efficient and low-cost implementations in Field Programmable Gate Arrays (FPGAs). We introduce a new time-discretization technique that uses request-acknowledge cycles between layers to allow the layer’s time execution to depend only upon the number of spikes. As a result, we achieve between 1.7x and 30x lower resource utilization and between 11x and 61x fewer spikes per inference than previous SNN implementations in FPGAs that rely on on-chip memory to store spike-time information and weight values. We demonstrate our approach using two benchmarks: MNIST digit recognition and a realistic radar and image sensory fusion for cropland classifications. Our results demonstrate that we can exploit the trade-off between accuracy, latency, and resource utilization at design time. Moreover, the use of low-cost FPGA platforms enables the deployment of several applications by satisfying the strict constraints of edge machine learning devices.
KW - spiking neural networks
KW - embedded hardware
KW - FPGA
UR - http://www.scopus.com/inward/record.url?scp=85138337734&partnerID=8YFLogxK
U2 - 10.1145/3546790.3546802
DO - 10.1145/3546790.3546802
M3 - Conference contribution
SN - 9781450397896
T3 - ACM International Conference Proceeding Series
SP - 1
EP - 8
BT - ICONS '22: Proceedings of the International Conference on Neuromorphic Systems 2022
PB - Association for Computing Machinery, Inc
CY - New York, NY, USA
T2 - 2022 International Conference on Neuromorphic Systems, ICONS 2022
Y2 - 27 July 2022 through 29 July 2022
ER -