The importance of low-power design is not just critical to portable devices but also to line powered equipment like TV products. Power dissipation strongly influences the price of the chip, since the packaging and cooling costs increase dramatically with increasing power dissipation. In this work, we analyze and optimize algorithm and architecture of a picture rate up-conversion module. We perform algorithm/architecture co-design in which we meet high quality specification while keeping the power dissipation low. In the algorithm front, we focus on the motion estimation which is computationally the most intensive part of the picture-rate up-conversion application. We analyze the following parameters of the motion estimation algorithm: The number of motion estimation iterations per input image pair and the image scanning order of individual iterations. Further, we apply novel pre-processing technique to address the issue of reducing the already extremely low number of motion vector candidate evaluations. However, optimal selection of motion vector candidates is a necessity to achieve high picture quality. In the architectural front, to cope with the large memory bandwidth requirements of the application, we use multi-level caching to exploit locality of reference. Further, we apply data compression to the image data stored in memory, to reduce the memory capacity and bandwidth requirements. Both the above techniques significantly reduce the overall power dissipation.
|Number of pages||15|
|Journal||Journal of VLSI Signal Processing|
|Publication status||Published - 2005|