TY - JOUR
T1 - An efficient on-chip NI offering guaranteed services, shared-memory abstraction, and flexible network configuration
AU - Radulescu, A.
AU - Dielissen, J.T.M.H.
AU - Pestana, S.G.
AU - Gangwal, O.P.
AU - Rijpkema, E.
AU - Wielage, P.
AU - Goossens, K.G.W.
PY - 2005
Y1 - 2005
N2 - In this paper, we present a network interface (NI) for an on-chip network. Our NI decouples computation from communication by offering a shared-memory abstraction, which is independent of the network implementation. We use a transaction-based protocol to achieve backward compatibility with existing bus protocols such as AXI, OCP, and DTL. Our NI has a modular architecture, which allows flexible instantiation. It provides both guaranteed and best-effort services via connections. These are configured via NI ports using the network itself, instead of a separate control interconnect. An example instance of this NI with four ports has an area of 0.25 mm2 after layout in 0. 13-µm technology, and runs at 500 MHz. U7 - Cited By (since 1996): 50 U7 - Export Date: 5 February 2010 U7 - Source: Scopus
AB - In this paper, we present a network interface (NI) for an on-chip network. Our NI decouples computation from communication by offering a shared-memory abstraction, which is independent of the network implementation. We use a transaction-based protocol to achieve backward compatibility with existing bus protocols such as AXI, OCP, and DTL. Our NI has a modular architecture, which allows flexible instantiation. It provides both guaranteed and best-effort services via connections. These are configured via NI ports using the network itself, instead of a separate control interconnect. An example instance of this NI with four ports has an area of 0.25 mm2 after layout in 0. 13-µm technology, and runs at 500 MHz. U7 - Cited By (since 1996): 50 U7 - Export Date: 5 February 2010 U7 - Source: Scopus
U2 - 10.1109/TCAD.2004.839493
DO - 10.1109/TCAD.2004.839493
M3 - Article
SN - 0278-0070
VL - 24
SP - 4
EP - 17
JO - IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
JF - IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
IS - 1
ER -