An efficient on-chip network interface offering guaranteed services, shared-memory abstraction, and flexible network configuration

A. Radulescu; J.T.M.H. Dielissen; K.G.W. Goossens; E. Rijpkema; P. Wielage

doi:10.1109/DATE.2004.1268998

An efficient on-chip network interface offering guaranteed services, shared-memory abstraction, and flexible network configuration

A. Radulescu
, J.T.M.H. Dielissen
, K.G.W. Goossens
, E. Rijpkema
, P. Wielage

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › Academic › peer-review

63 Citations (Scopus)

Abstract

In this paper we present a network interface for an on-chip network. Our network interface decouples computation from communication by offering a shared-memory abstraction, which is independent of the network implementation. We use a transaction-based protocol to achieve backward compatibility with existing bus protocols such as AXI, OCP and DTL Our network interface has a modular architecture, which allows flexible instantiation. It provides both guaranteed and best-effort services via connections. These are configured via network interface ports using the network itself, instead of a separate control interconnect. An example instance of this network interface with 4 ports has an area of 0.143mm² in a 0.123µm technology, and runs at 500 MHz.

Original language	English
Title of host publication	Design, Automation and Test in Europe Conference and Exhibition, DATE 04, 16 February 2004 through 20 February 2004, Paris
Place of Publication	Piscataway
Publisher	Institute of Electrical and Electronics Engineers
Pages	878-883
ISBN (Print)	0-7695-2085-5
DOIs	https://doi.org/10.1109/DATE.2004.1268998
Publication status	Published - 2004
Externally published	Yes
Event	7th Design, Automation and Test in Europe Conference and Exposition (DATE 2004) - Paris, France Duration: 16 Feb 2004 → 20 Feb 2004 Conference number: 7

Conference

Conference	7th Design, Automation and Test in Europe Conference and Exposition (DATE 2004)
Abbreviated title	DATE 2004
Country/Territory	France
City	Paris
Period	16/02/04 → 20/02/04

Access to Document

10.1109/DATE.2004.1268998

Cite this

Radulescu, A., Dielissen, J. T. M. H., Goossens, K. G. W., Rijpkema, E., & Wielage, P. (2004). An efficient on-chip network interface offering guaranteed services, shared-memory abstraction, and flexible network configuration. In Design, Automation and Test in Europe Conference and Exhibition, DATE 04, 16 February 2004 through 20 February 2004, Paris (pp. 878-883). Institute of Electrical and Electronics Engineers. https://doi.org/10.1109/DATE.2004.1268998

Radulescu, A. ; Dielissen, J.T.M.H. ; Goossens, K.G.W. et al. / An efficient on-chip network interface offering guaranteed services, shared-memory abstraction, and flexible network configuration. Design, Automation and Test in Europe Conference and Exhibition, DATE 04, 16 February 2004 through 20 February 2004, Paris. Piscataway : Institute of Electrical and Electronics Engineers, 2004. pp. 878-883

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title = "An efficient on-chip network interface offering guaranteed services, shared-memory abstraction, and flexible network configuration",

abstract = "In this paper we present a network interface for an on-chip network. Our network interface decouples computation from communication by offering a shared-memory abstraction, which is independent of the network implementation. We use a transaction-based protocol to achieve backward compatibility with existing bus protocols such as AXI, OCP and DTL Our network interface has a modular architecture, which allows flexible instantiation. It provides both guaranteed and best-effort services via connections. These are configured via network interface ports using the network itself, instead of a separate control interconnect. An example instance of this network interface with 4 ports has an area of 0.143mm2 in a 0.123µm technology, and runs at 500 MHz.",

author = "A. Radulescu and J.T.M.H. Dielissen and K.G.W. Goossens and E. Rijpkema and P. Wielage",

year = "2004",

doi = "10.1109/DATE.2004.1268998",

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note = "7th Design, Automation and Test in Europe Conference and Exposition (DATE 2004), DATE 2004 ; Conference date: 16-02-2004 Through 20-02-2004",

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Radulescu, A, Dielissen, JTMH, Goossens, KGW, Rijpkema, E & Wielage, P 2004, An efficient on-chip network interface offering guaranteed services, shared-memory abstraction, and flexible network configuration. in Design, Automation and Test in Europe Conference and Exhibition, DATE 04, 16 February 2004 through 20 February 2004, Paris. Institute of Electrical and Electronics Engineers, Piscataway, pp. 878-883, 7th Design, Automation and Test in Europe Conference and Exposition (DATE 2004), Paris, France, 16/02/04. https://doi.org/10.1109/DATE.2004.1268998

An efficient on-chip network interface offering guaranteed services, shared-memory abstraction, and flexible network configuration. / Radulescu, A.; Dielissen, J.T.M.H.; Goossens, K.G.W. et al.
Design, Automation and Test in Europe Conference and Exhibition, DATE 04, 16 February 2004 through 20 February 2004, Paris. Piscataway: Institute of Electrical and Electronics Engineers, 2004. p. 878-883.

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › Academic › peer-review

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N2 - In this paper we present a network interface for an on-chip network. Our network interface decouples computation from communication by offering a shared-memory abstraction, which is independent of the network implementation. We use a transaction-based protocol to achieve backward compatibility with existing bus protocols such as AXI, OCP and DTL Our network interface has a modular architecture, which allows flexible instantiation. It provides both guaranteed and best-effort services via connections. These are configured via network interface ports using the network itself, instead of a separate control interconnect. An example instance of this network interface with 4 ports has an area of 0.143mm2 in a 0.123µm technology, and runs at 500 MHz.

AB - In this paper we present a network interface for an on-chip network. Our network interface decouples computation from communication by offering a shared-memory abstraction, which is independent of the network implementation. We use a transaction-based protocol to achieve backward compatibility with existing bus protocols such as AXI, OCP and DTL Our network interface has a modular architecture, which allows flexible instantiation. It provides both guaranteed and best-effort services via connections. These are configured via network interface ports using the network itself, instead of a separate control interconnect. An example instance of this network interface with 4 ports has an area of 0.143mm2 in a 0.123µm technology, and runs at 500 MHz.

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M3 - Conference contribution

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SP - 878

EP - 883

BT - Design, Automation and Test in Europe Conference and Exhibition, DATE 04, 16 February 2004 through 20 February 2004, Paris

PB - Institute of Electrical and Electronics Engineers

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T2 - 7th Design, Automation and Test in Europe Conference and Exposition (DATE 2004)

Y2 - 16 February 2004 through 20 February 2004

ER -

Radulescu A, Dielissen JTMH, Goossens KGW, Rijpkema E, Wielage P. An efficient on-chip network interface offering guaranteed services, shared-memory abstraction, and flexible network configuration. In Design, Automation and Test in Europe Conference and Exhibition, DATE 04, 16 February 2004 through 20 February 2004, Paris. Piscataway: Institute of Electrical and Electronics Engineers. 2004. p. 878-883 doi: 10.1109/DATE.2004.1268998

An efficient on-chip network interface offering guaranteed services, shared-memory abstraction, and flexible network configuration

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