An efficient lateral channel profiling of poly-SiGe-gated PMOSFET's for 0.1 μm CMOS low-voltage applications

Y. V. Ponomarev, P. A. Stolk, A. C.M.C. van Brandenburg, C. J.J. Dachs, M. Kaiser, A. H. Montree, R. Roes, J. Schmitz, P. H. Woerlee

Research output: Chapter in Book/Report/Conference proceedingConference contributionAcademicpeer-review

4 Citations (Scopus)

Abstract

An aggressive lateral MOS channel profiling combined with gate workfunction engineering for sub-0.13μm generation PMOSFETs oriented for low-voltage operations was studied. In this scheme, the Ge fraction in poly-SiGe gate was used to control VT, while short channel effects (SCEs) were completely suppressed down to 100nm gate lengths by heavily-doped, sharp envelopes around the source/drain. The fabricated bulk devices exhibit low DIBL, no VT roll-off behavior, and 67mV/dec sub-VT voltage swing. Process variation analysis confirmed the high manufacturing potential for the approach suggested.

Original languageEnglish
Title of host publication1999 Symposium on VLSI Technology. Digest of Technical Papers
Place of PublicationPiscataway
PublisherInstitute of Electrical and Electronics Engineers
Pages65-66
Number of pages2
ISBN (Print)4-930813-93-X
DOIs
Publication statusPublished - 1 Dec 1999
Externally publishedYes
Event1999 Symposium on VLSI Technology - Kyoto, Jpn
Duration: 14 Jun 199916 Jun 1999

Conference

Conference1999 Symposium on VLSI Technology
CityKyoto, Jpn
Period14/06/9916/06/99

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    Ponomarev, Y. V., Stolk, P. A., van Brandenburg, A. C. M. C., Dachs, C. J. J., Kaiser, M., Montree, A. H., Roes, R., Schmitz, J., & Woerlee, P. H. (1999). An efficient lateral channel profiling of poly-SiGe-gated PMOSFET's for 0.1 μm CMOS low-voltage applications. In 1999 Symposium on VLSI Technology. Digest of Technical Papers (pp. 65-66). Institute of Electrical and Electronics Engineers. https://doi.org/10.1109/VLSIT.1999.799342