An efficient lateral channel profiling of poly-SiGe-gated PMOSFET's for 0.1 μm CMOS low-voltage applications

Y. V. Ponomarev; P. A. Stolk; A. C.M.C. van Brandenburg; C. J.J. Dachs; M. Kaiser; A. H. Montree; R. Roes; J. Schmitz; P. H. Woerlee

doi:10.1109/VLSIT.1999.799342

An efficient lateral channel profiling of poly-SiGe-gated PMOSFET's for 0.1 μm CMOS low-voltage applications

Y. V. Ponomarev, P. A. Stolk, A. C.M.C. van Brandenburg, C. J.J. Dachs, M. Kaiser, A. H. Montree, R. Roes, J. Schmitz, P. H. Woerlee

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › Academic › peer-review

4 Citations (SciVal)

Abstract

An aggressive lateral MOS channel profiling combined with gate workfunction engineering for sub-0.13μm generation PMOSFETs oriented for low-voltage operations was studied. In this scheme, the Ge fraction in poly-SiGe gate was used to control V_T, while short channel effects (SCEs) were completely suppressed down to 100nm gate lengths by heavily-doped, sharp envelopes around the source/drain. The fabricated bulk devices exhibit low DIBL, no V_T roll-off behavior, and 67mV/dec sub-V_T voltage swing. Process variation analysis confirmed the high manufacturing potential for the approach suggested.

Original language	English
Title of host publication	1999 Symposium on VLSI Technology. Digest of Technical Papers
Place of Publication	Piscataway
Publisher	Institute of Electrical and Electronics Engineers
Pages	65-66
Number of pages	2
ISBN (Print)	4-930813-93-X
DOIs	https://doi.org/10.1109/VLSIT.1999.799342
Publication status	Published - 1 Dec 1999
Externally published	Yes
Event	1999 Symposium on VLSI Technology - Kyoto, Jpn Duration: 14 Jun 1999 → 16 Jun 1999

Conference

Conference	1999 Symposium on VLSI Technology
City	Kyoto, Jpn
Period	14/06/99 → 16/06/99

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10.1109/VLSIT.1999.799342

Cite this

Ponomarev, Y. V., Stolk, P. A., van Brandenburg, A. C. M. C., Dachs, C. J. J., Kaiser, M., Montree, A. H., Roes, R., Schmitz, J., & Woerlee, P. H. (1999). An efficient lateral channel profiling of poly-SiGe-gated PMOSFET's for 0.1 μm CMOS low-voltage applications. In 1999 Symposium on VLSI Technology. Digest of Technical Papers (pp. 65-66). Institute of Electrical and Electronics Engineers. https://doi.org/10.1109/VLSIT.1999.799342

@inproceedings{6cb8a90e00bf4d14ad0d2605a8dff1df,

title = "An efficient lateral channel profiling of poly-SiGe-gated PMOSFET's for 0.1 μm CMOS low-voltage applications",

abstract = "An aggressive lateral MOS channel profiling combined with gate workfunction engineering for sub-0.13μm generation PMOSFETs oriented for low-voltage operations was studied. In this scheme, the Ge fraction in poly-SiGe gate was used to control VT, while short channel effects (SCEs) were completely suppressed down to 100nm gate lengths by heavily-doped, sharp envelopes around the source/drain. The fabricated bulk devices exhibit low DIBL, no VT roll-off behavior, and 67mV/dec sub-VT voltage swing. Process variation analysis confirmed the high manufacturing potential for the approach suggested.",

author = "Ponomarev, {Y. V.} and Stolk, {P. A.} and {van Brandenburg}, {A. C.M.C.} and Dachs, {C. J.J.} and M. Kaiser and Montree, {A. H.} and R. Roes and J. Schmitz and Woerlee, {P. H.}",

year = "1999",

month = dec,

day = "1",

doi = "10.1109/VLSIT.1999.799342",

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pages = "65--66",

booktitle = "1999 Symposium on VLSI Technology. Digest of Technical Papers",

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note = "1999 Symposium on VLSI Technology ; Conference date: 14-06-1999 Through 16-06-1999",

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Ponomarev, YV, Stolk, PA, van Brandenburg, ACMC, Dachs, CJJ, Kaiser, M, Montree, AH, Roes, R, Schmitz, J & Woerlee, PH 1999, An efficient lateral channel profiling of poly-SiGe-gated PMOSFET's for 0.1 μm CMOS low-voltage applications. in 1999 Symposium on VLSI Technology. Digest of Technical Papers. Institute of Electrical and Electronics Engineers, Piscataway, pp. 65-66, 1999 Symposium on VLSI Technology, Kyoto, Jpn, 14/06/99. https://doi.org/10.1109/VLSIT.1999.799342

An efficient lateral channel profiling of poly-SiGe-gated PMOSFET's for 0.1 μm CMOS low-voltage applications. / Ponomarev, Y. V.; Stolk, P. A.; van Brandenburg, A. C.M.C. et al.
1999 Symposium on VLSI Technology. Digest of Technical Papers. Piscataway: Institute of Electrical and Electronics Engineers, 1999. p. 65-66.

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › Academic › peer-review

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AU - Ponomarev, Y. V.

AU - Stolk, P. A.

AU - van Brandenburg, A. C.M.C.

AU - Dachs, C. J.J.

AU - Kaiser, M.

AU - Montree, A. H.

AU - Roes, R.

AU - Schmitz, J.

AU - Woerlee, P. H.

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N2 - An aggressive lateral MOS channel profiling combined with gate workfunction engineering for sub-0.13μm generation PMOSFETs oriented for low-voltage operations was studied. In this scheme, the Ge fraction in poly-SiGe gate was used to control VT, while short channel effects (SCEs) were completely suppressed down to 100nm gate lengths by heavily-doped, sharp envelopes around the source/drain. The fabricated bulk devices exhibit low DIBL, no VT roll-off behavior, and 67mV/dec sub-VT voltage swing. Process variation analysis confirmed the high manufacturing potential for the approach suggested.

AB - An aggressive lateral MOS channel profiling combined with gate workfunction engineering for sub-0.13μm generation PMOSFETs oriented for low-voltage operations was studied. In this scheme, the Ge fraction in poly-SiGe gate was used to control VT, while short channel effects (SCEs) were completely suppressed down to 100nm gate lengths by heavily-doped, sharp envelopes around the source/drain. The fabricated bulk devices exhibit low DIBL, no VT roll-off behavior, and 67mV/dec sub-VT voltage swing. Process variation analysis confirmed the high manufacturing potential for the approach suggested.

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BT - 1999 Symposium on VLSI Technology. Digest of Technical Papers

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ER -

Ponomarev YV, Stolk PA, van Brandenburg ACMC, Dachs CJJ, Kaiser M, Montree AH et al. An efficient lateral channel profiling of poly-SiGe-gated PMOSFET's for 0.1 μm CMOS low-voltage applications. In 1999 Symposium on VLSI Technology. Digest of Technical Papers. Piscataway: Institute of Electrical and Electronics Engineers. 1999. p. 65-66 doi: 10.1109/VLSIT.1999.799342

An efficient lateral channel profiling of poly-SiGe-gated PMOSFET's for 0.1 μm CMOS low-voltage applications

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