An efficient FPGA implementation of HEVC intra prediction

Hasan Azgin; Ahmet Can Mert; Ercan Kalali; Ilker Hamzaoglu

doi:10.1109/ICCE.2018.8326332

An efficient FPGA implementation of HEVC intra prediction

Hasan Azgin, Ahmet Can Mert, Ercan Kalali, Ilker Hamzaoglu

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › Academic › peer-review

10 Citations (Scopus)

Abstract

Intra prediction algorithm used in High Efficiency Video Coding (HEVC) standard has very high computational complexity. In this paper, an efficient FPGA implementation of HEVC intra prediction is proposed for 4×4, 8×8, 16×16 and 32×32 angular prediction modes. In the proposed FPGA implementation, one intra angular prediction equation is implemented using one DSP block in FPGA. The proposed FPGA implementation, in the worst case, can process 55 Full HD (1920×1080) video frames per second. It has up to 34.66% less energy consumption than the original FPGA implementation of HEVC intra prediction. Therefore, it can be used in portable consumer electronics products that require a real-time HEVC encoder.

Original language	English
Title of host publication	2018 IEEE International Conference on Consumer Electronics (ICCE)
Editors	Saraju P. Mohanty, Peter Corcoran, Hai Li, Anirban Sengupta, Jong-Hyouk Lee
Publisher	Institute of Electrical and Electronics Engineers
Pages	1-5
Number of pages	5
ISBN (Electronic)	978-1-5386-3025-9
DOIs	https://doi.org/10.1109/ICCE.2018.8326332
Publication status	Published - 29 Mar 2018
Externally published	Yes
Event	2018 IEEE International Conference on Consumer Electronics, ICCE 2018 - Las Vegas, United States Duration: 12 Jan 2018 → 14 Jan 2018 Conference number: 36

Conference

Conference	2018 IEEE International Conference on Consumer Electronics, ICCE 2018
Abbreviated title	ICCE 2018
Country/Territory	United States
City	Las Vegas
Period	12/01/18 → 14/01/18

Keywords

HEVC
Intra Prediction
Hardware Implementation
FPGA

UN SDGs

This output contributes to the following UN Sustainable Development Goals (SDGs)

Access to Document

10.1109/ICCE.2018.8326332

Cite this

Azgin, H., Mert, A. C., Kalali, E., & Hamzaoglu, I. (2018). An efficient FPGA implementation of HEVC intra prediction. In S. P. Mohanty, P. Corcoran, H. Li, A. Sengupta, & J.-H. Lee (Eds.), 2018 IEEE International Conference on Consumer Electronics (ICCE) (pp. 1-5). Article 8326332 Institute of Electrical and Electronics Engineers. https://doi.org/10.1109/ICCE.2018.8326332

@inproceedings{85873ff2cd1c4ddcbfd79a17c3882336,

title = "An efficient FPGA implementation of HEVC intra prediction",

abstract = "Intra prediction algorithm used in High Efficiency Video Coding (HEVC) standard has very high computational complexity. In this paper, an efficient FPGA implementation of HEVC intra prediction is proposed for 4×4, 8×8, 16×16 and 32×32 angular prediction modes. In the proposed FPGA implementation, one intra angular prediction equation is implemented using one DSP block in FPGA. The proposed FPGA implementation, in the worst case, can process 55 Full HD (1920×1080) video frames per second. It has up to 34.66% less energy consumption than the original FPGA implementation of HEVC intra prediction. Therefore, it can be used in portable consumer electronics products that require a real-time HEVC encoder.",

keywords = "HEVC, Intra Prediction, Hardware Implementation, FPGA",

author = "Hasan Azgin and Mert, {Ahmet Can} and Ercan Kalali and Ilker Hamzaoglu",

note = "Publisher Copyright: {\textcopyright} 2018 IEEE.; 2018 IEEE International Conference on Consumer Electronics, ICCE 2018, ICCE 2018 ; Conference date: 12-01-2018 Through 14-01-2018",

year = "2018",

month = mar,

day = "29",

doi = "10.1109/ICCE.2018.8326332",

language = "English",

pages = "1--5",

editor = "Mohanty, {Saraju P.} and Peter Corcoran and Hai Li and Anirban Sengupta and Jong-Hyouk Lee",

booktitle = "2018 IEEE International Conference on Consumer Electronics (ICCE)",

publisher = "Institute of Electrical and Electronics Engineers",

address = "United States",

}

Azgin, H, Mert, AC, Kalali, E & Hamzaoglu, I 2018, An efficient FPGA implementation of HEVC intra prediction. in SP Mohanty, P Corcoran, H Li, A Sengupta & J-H Lee (eds), 2018 IEEE International Conference on Consumer Electronics (ICCE)., 8326332, Institute of Electrical and Electronics Engineers, pp. 1-5, 2018 IEEE International Conference on Consumer Electronics, ICCE 2018, Las Vegas, Nevada, United States, 12/01/18. https://doi.org/10.1109/ICCE.2018.8326332

An efficient FPGA implementation of HEVC intra prediction. / Azgin, Hasan; Mert, Ahmet Can; Kalali, Ercan et al.
2018 IEEE International Conference on Consumer Electronics (ICCE). ed. / Saraju P. Mohanty; Peter Corcoran; Hai Li; Anirban Sengupta; Jong-Hyouk Lee. Institute of Electrical and Electronics Engineers, 2018. p. 1-5 8326332.

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › Academic › peer-review

TY - GEN

T1 - An efficient FPGA implementation of HEVC intra prediction

AU - Azgin, Hasan

AU - Mert, Ahmet Can

AU - Kalali, Ercan

AU - Hamzaoglu, Ilker

N1 - Conference code: 36

PY - 2018/3/29

Y1 - 2018/3/29

N2 - Intra prediction algorithm used in High Efficiency Video Coding (HEVC) standard has very high computational complexity. In this paper, an efficient FPGA implementation of HEVC intra prediction is proposed for 4×4, 8×8, 16×16 and 32×32 angular prediction modes. In the proposed FPGA implementation, one intra angular prediction equation is implemented using one DSP block in FPGA. The proposed FPGA implementation, in the worst case, can process 55 Full HD (1920×1080) video frames per second. It has up to 34.66% less energy consumption than the original FPGA implementation of HEVC intra prediction. Therefore, it can be used in portable consumer electronics products that require a real-time HEVC encoder.

AB - Intra prediction algorithm used in High Efficiency Video Coding (HEVC) standard has very high computational complexity. In this paper, an efficient FPGA implementation of HEVC intra prediction is proposed for 4×4, 8×8, 16×16 and 32×32 angular prediction modes. In the proposed FPGA implementation, one intra angular prediction equation is implemented using one DSP block in FPGA. The proposed FPGA implementation, in the worst case, can process 55 Full HD (1920×1080) video frames per second. It has up to 34.66% less energy consumption than the original FPGA implementation of HEVC intra prediction. Therefore, it can be used in portable consumer electronics products that require a real-time HEVC encoder.

KW - HEVC

KW - Intra Prediction

KW - Hardware Implementation

KW - FPGA

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U2 - 10.1109/ICCE.2018.8326332

DO - 10.1109/ICCE.2018.8326332

M3 - Conference contribution

SP - 1

EP - 5

BT - 2018 IEEE International Conference on Consumer Electronics (ICCE)

A2 - Mohanty, Saraju P.

A2 - Corcoran, Peter

A2 - Li, Hai

A2 - Sengupta, Anirban

A2 - Lee, Jong-Hyouk

PB - Institute of Electrical and Electronics Engineers

T2 - 2018 IEEE International Conference on Consumer Electronics, ICCE 2018

Y2 - 12 January 2018 through 14 January 2018

ER -

An efficient FPGA implementation of HEVC intra prediction

Abstract

Conference

Keywords

UN SDGs

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