An automated technique to generate relocatable partial bitstreams for Xilinx FPGAs

R. Oomen, Tuan Nguyen, A. Kumar, H. Corporaal

Research output: Chapter in Book/Report/Conference proceedingConference contributionAcademicpeer-review

6 Citations (Scopus)

Abstract

Partial reconfiguration is a technique used to increase the flexibility of an FPGA-based system by reprogramming parts of the system dynamically without interrupting the operation of the other modules. Despite the runtime benefits offered by partially reconfigurable (PR) systems, creating and storing partial bitstreams (PBs) are becoming major concerns for system architects when the numbers of reconfigurable partitions (RPs) and PR modules (PRMs) increase. It takes significant amount of time to generate the PBs for PR systems with large number of RPs and PRMs. More importantly, when the mapping relationship between PRMs and RPs is many-to-many, several almost-identical PBs of one PRM must be stored separately which leads to inefficient utilization of the memory storage. Therefore, bitstream relocation is drawing interests from the research community as a viable solution. Yet almost none of the works are able to demonstrate a coherent method to not only create relocatable PBs for complex and large PRMs in variable-size RPs but also how to do that automatically to free the designer from the tedious and error prone manual processes. In this paper, we propose a new technique to fill that gap. The method is successfully developed for Xilinx Virtex 7 devices using Vivado design tool flow.

Original languageEnglish
Title of host publication25th International Conference on Field Programmable Logic and Applications, FPL 2015
Place of PublicationPiscataway
PublisherInstitute of Electrical and Electronics Engineers
Pages1-4
Number of pages4
ISBN (Electronic)978-0-9934-2800-5
DOIs
Publication statusPublished - 7 Oct 2015
Event25th International Conference on Field Programmable Logic and Applications (FPL 2015), September 2-4, 2015, London, United Kingdom - London, United Kingdom
Duration: 2 Sep 20154 Sep 2015
http://www.fpl2015.org/

Conference

Conference25th International Conference on Field Programmable Logic and Applications (FPL 2015), September 2-4, 2015, London, United Kingdom
Abbreviated titleFPL 2015
CountryUnited Kingdom
CityLondon
Period2/09/154/09/15
Internet address

Keywords

  • bitstream relocation
  • FPGA
  • partial reconfiguration
  • Virtex-7
  • Vivado

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