An automated flow to map throughput constrained applications to a MPSoC

R. Jordans, F.M. Siyoum, S. Stuijk, A. Kumar, H. Corporaal

Research output: Chapter in Book/Report/Conference proceedingConference contributionAcademicpeer-review

6 Citations (Scopus)
59 Downloads (Pure)


This paper describes a design flow to map throughput constrained applications on a Multi-processor System-on-Chip (MPSoC). It integrates several state-of-the-art mapping and synthesis tools into an automated tool flow. This flow takes as input a throughput constrained application, modeled with a synchronous dataflow graph, a C-based implementation for each actor in the graph, and a template based architecture description. Using these inputs, the tool flow generates an MPSoC platform tailored to the application requirements and it subsequently maps the application to this platform. The output of the flow is an FPGA programmable bit file. An easily extensible template based architecture is presented, this architecture allows fast and flexible generation of a predictable platform that can be synthesized using the presented tool flow. The effectiveness of the tool flow is demonstrated by mapping an MJPEG-decoder onto our MPSoC platform. This case study shows that our flow is able to provide a tight, conservative bound on the worst-case throughput of the FPGA implementation. The presented tool flow is freely available at
Original languageEnglish
Title of host publicationBringing Theory to Practice : Predictability and Performance in Embedded Systems, 14-18 March 2011, Grenoble, Switzerland
EditorsP. Lucas, L. Thiele, B. Triquet, T. Ungerer, R. Wilhelm
Place of PublicationLeibniz
PublisherDagstuhl Publishing
ISBN (Print)978-3-939897-28-6
Publication statusPublished - 2011
Eventconference; PPES'11 -
Duration: 1 Jan 2011 → …

Publication series

NameOpenAccess Series in Informatics
ISSN (Print)2190-6807


Conferenceconference; PPES'11
Period1/01/11 → …


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