An area-and-power-efficient 8.4-bit ENOB 30 MS/s SAR ADC in 65 nm CMOS

Y. Xu (Corresponding author), P.J.A. Harpe, T. Ytterdal

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1 Citation (Scopus)
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Abstract

Area and power consumption are two main concerns for the electronics towards the digitalization of in-probe 3D ultrasound imaging systems. This work presents a 10-bit 30 MS/s successive approximation register analog-to-digital converter, which achieves good area efficiency as well as power efficiency, by using a symmetrical MSB-capacitor-split capacitor array with customized small-value finger capacitors. Moreover, simplified dynamic digital logic and a dynamic comparator have been designed. Fabricated in a 65 nm CMOS technology, the core circuit only occupies 0.016 mm2. The ADC achieves a signal-to-noise ratio of 52.2 dB, and consumes 61.3 μW at 30 MS/s from a 1 V supply voltage, resulting in a figure of merit (FoM) of 6.2 fJ/conversion-step. The FoM defined by including the area is 0.1 mm2 fJ/conversion-step.

Original languageEnglish
Pages (from-to)17-27
Number of pages11
JournalAnalog Integrated Circuits and Signal Processing
Volume90
Issue number1
DOIs
Publication statusPublished - 1 Jan 2017

Keywords

  • Analog-to-digital converter (ADC)
  • Area efficiency
  • Power efficiency
  • Successive approximation register (SAR)
  • Ultrasound imaging systems

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