Abstract
Accurate timing characterization of flip-flops is critical for robust circuit design. Conventionally, setup time and hold time are characterized independently, which results in pessimistic/optimistic designs. To reduce this pessimism/optimism, the interdependency between setup/hold-time has to be taken into account. Fast and accurate characterization of the setup/hold-time interdependency is however a challenging task. In this paper, an analytical model is proposed to capture the setup/hold-time interdependency in a conventional master-slave flip-flop. The accuracy of the proposed model is ∼10× higher than the previously published characterization methods. Furthermore, a flow is proposed to find the parameters of the model with ∼2.5× shorter computation time compared to the existing methods.
Original language | English |
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Title of host publication | Proceedings of the 18th International Symposium on Quality Electronic Design, ISQED 2017 |
Place of Publication | Piscataway |
Publisher | Institute of Electrical and Electronics Engineers |
Pages | 209-214 |
Number of pages | 6 |
ISBN (Electronic) | 978-1-5090-5404-6 |
DOIs | |
Publication status | Published - 2 May 2017 |
Event | 18th International Symposium on Quality Electronic Design, ISQED 2017 - Santa Clara, United States Duration: 14 Mar 2017 → 15 Mar 2017 |
Conference
Conference | 18th International Symposium on Quality Electronic Design, ISQED 2017 |
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Country/Territory | United States |
City | Santa Clara |
Period | 14/03/17 → 15/03/17 |