An activity monitor for power/performance tuning of CMOS digital circuits

J. Rius, J. Pineda de Gyvez, M. Meijer

Research output: Chapter in Book/Report/Conference proceedingConference contributionAcademicpeer-review

1 Citation (Scopus)
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The requirement to control each possible degree of freedom of digital circuits becomes a necessity in deep submicron technologies. This requires getting a set of monitors to measure each one of the parameters of interest. This paper describes a monitor fabricated in a 90nm CMOS technology which is able to estimate the circuit activity. The output of such monitor can be used as a tool to decide how to adjust the circuit working conditions to get the best power/performance circuit response. The paper presents the implementation and experimental results of a test chip including such monitor.
Original languageEnglish
Title of host publicationProceedings of PATMOS 2005, Leuven
Publication statusPublished - 2005


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