The requirement to control each possible degree of freedom of digital circuits becomes a necessity in deep submicron technologies. This requires getting a set of monitors to measure each one of the parameters of interest. This paper describes a monitor fabricated in a 90nm CMOS technology which is able to estimate the circuit activity. The output of such monitor can be used as a tool to decide how to adjust the circuit working conditions to get the best power/performance circuit response. The paper presents the implementation and experimental results of a test chip including such monitor.
|Title of host publication||Proceedings of PATMOS 2005, Leuven|
|Publication status||Published - 2005|
Rius, J., Pineda de Gyvez, J., & Meijer, M. (2005). An activity monitor for power/performance tuning of CMOS digital circuits. In Proceedings of PATMOS 2005, Leuven (pp. 187-196) https://doi.org/10.1007/11556930_20