An activity monitor for power/performance tuning of CMOS digital circuits

J. Rius; J. Pineda de Gyvez; M. Meijer

doi:10.1007/11556930_20

An activity monitor for power/performance tuning of CMOS digital circuits

J. Rius, J. Pineda de Gyvez, M. Meijer

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Abstract

The requirement to control each possible degree of freedom of digital circuits becomes a necessity in deep submicron technologies. This requires getting a set of monitors to measure each one of the parameters of interest. This paper describes a monitor fabricated in a 90nm CMOS technology which is able to estimate the circuit activity. The output of such monitor can be used as a tool to decide how to adjust the circuit working conditions to get the best power/performance circuit response. The paper presents the implementation and experimental results of a test chip including such monitor.

Original language	English
Title of host publication	Proceedings of PATMOS 2005, Leuven
Pages	187-196
DOIs	https://doi.org/10.1007/11556930_20
Publication status	Published - 2005

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title = "An activity monitor for power/performance tuning of CMOS digital circuits",

abstract = "The requirement to control each possible degree of freedom of digital circuits becomes a necessity in deep submicron technologies. This requires getting a set of monitors to measure each one of the parameters of interest. This paper describes a monitor fabricated in a 90nm CMOS technology which is able to estimate the circuit activity. The output of such monitor can be used as a tool to decide how to adjust the circuit working conditions to get the best power/performance circuit response. The paper presents the implementation and experimental results of a test chip including such monitor.",

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AB - The requirement to control each possible degree of freedom of digital circuits becomes a necessity in deep submicron technologies. This requires getting a set of monitors to measure each one of the parameters of interest. This paper describes a monitor fabricated in a 90nm CMOS technology which is able to estimate the circuit activity. The output of such monitor can be used as a tool to decide how to adjust the circuit working conditions to get the best power/performance circuit response. The paper presents the implementation and experimental results of a test chip including such monitor.

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DO - 10.1007/11556930_20

M3 - Conference contribution

SP - 187

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BT - Proceedings of PATMOS 2005, Leuven

ER -

An activity monitor for power/performance tuning of CMOS digital circuits

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