An 8MIPS CMOS digital signal processor

J. van Meerbergen; F. Welten; F. v. Wijk; J. Stoter; J. Huisken; A. Delaruelle; K.V. Eerdewijk; J. Schmid; J. Wittek

doi:10.1109/ISSCC.1986.1156982

An 8MIPS CMOS digital signal processor

J. van Meerbergen, F. Welten, F. v. Wijk, J. Stoter, J. Huisken, A. Delaruelle, K.V. Eerdewijk, J. Schmid, J. Wittek

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › Academic › peer-review

Abstract

A 2μm digital signal processor with a 125ns instruction cycle will be described. It contains two 16b data buses, executes a 40b orthogonal instruction set and supports up to six concurrent arithmetic and data-move operations in each instruction.

Original language	English
Title of host publication	1986 IEEE International Solid-State Circuits Conference
Subtitle of host publication	Digest of Technical Papers
Publisher	Institute of Electrical and Electronics Engineers
Pages	84-85
Number of pages	2
Volume	XXIX
DOIs	https://doi.org/10.1109/ISSCC.1986.1156982
Publication status	Published - 6 Jan 2003
Externally published	Yes
Event	1986 IEEE International Conference on Solid-State Circuits, ISSCC 1986 - Anaheim, United States Duration: 19 Feb 1986 → 21 Feb 1986

Conference

Conference	1986 IEEE International Conference on Solid-State Circuits, ISSCC 1986
Abbreviated title	ISSCC 1986
Country/Territory	United States
City	Anaheim
Period	19/02/86 → 21/02/86

Keywords

CMOS process
Digital signal processors
Random access memory
Read-write memory
Registers
Read only memory
Data buses
Hardware
Pipelines
Arithmetic

Access to Document

10.1109/ISSCC.1986.1156982

Cite this

van Meerbergen, J., Welten, F., v. Wijk, F., Stoter, J., Huisken, J., Delaruelle, A., Eerdewijk, K. V., Schmid, J., & Wittek, J. (2003). An 8MIPS CMOS digital signal processor. In 1986 IEEE International Solid-State Circuits Conference: Digest of Technical Papers (Vol. XXIX, pp. 84-85). Article 1156982 Institute of Electrical and Electronics Engineers. https://doi.org/10.1109/ISSCC.1986.1156982

@inproceedings{69a9de630e904526b0d0e96e0e26844b,

title = "An 8MIPS CMOS digital signal processor",

abstract = "A 2μm digital signal processor with a 125ns instruction cycle will be described. It contains two 16b data buses, executes a 40b orthogonal instruction set and supports up to six concurrent arithmetic and data-move operations in each instruction.",

keywords = "CMOS process, Digital signal processors, Random access memory, Read-write memory, Registers, Read only memory, Data buses, Hardware, Pipelines, Arithmetic",

author = "{van Meerbergen}, J. and F. Welten and {v. Wijk}, F. and J. Stoter and J. Huisken and A. Delaruelle and K.V. Eerdewijk and J. Schmid and J. Wittek",

year = "2003",

month = jan,

day = "6",

doi = "10.1109/ISSCC.1986.1156982",

language = "English",

volume = "XXIX",

pages = "84--85",

booktitle = "1986 IEEE International Solid-State Circuits Conference",

publisher = "Institute of Electrical and Electronics Engineers",

address = "United States",

note = "1986 IEEE International Conference on Solid-State Circuits, ISSCC 1986, ISSCC 1986 ; Conference date: 19-02-1986 Through 21-02-1986",

}

van Meerbergen, J, Welten, F, v. Wijk, F, Stoter, J, Huisken, J, Delaruelle, A, Eerdewijk, KV, Schmid, J & Wittek, J 2003, An 8MIPS CMOS digital signal processor. in 1986 IEEE International Solid-State Circuits Conference: Digest of Technical Papers. vol. XXIX, 1156982, Institute of Electrical and Electronics Engineers, pp. 84-85, 1986 IEEE International Conference on Solid-State Circuits, ISSCC 1986, Anaheim, California, United States, 19/02/86. https://doi.org/10.1109/ISSCC.1986.1156982

An 8MIPS CMOS digital signal processor. / van Meerbergen, J.; Welten, F.; v. Wijk, F. et al.
1986 IEEE International Solid-State Circuits Conference: Digest of Technical Papers. Vol. XXIX Institute of Electrical and Electronics Engineers, 2003. p. 84-85 1156982.

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › Academic › peer-review

TY - GEN

T1 - An 8MIPS CMOS digital signal processor

AU - van Meerbergen, J.

AU - Welten, F.

AU - v. Wijk, F.

AU - Stoter, J.

AU - Huisken, J.

AU - Delaruelle, A.

AU - Eerdewijk, K.V.

AU - Schmid, J.

AU - Wittek, J.

PY - 2003/1/6

Y1 - 2003/1/6

N2 - A 2μm digital signal processor with a 125ns instruction cycle will be described. It contains two 16b data buses, executes a 40b orthogonal instruction set and supports up to six concurrent arithmetic and data-move operations in each instruction.

AB - A 2μm digital signal processor with a 125ns instruction cycle will be described. It contains two 16b data buses, executes a 40b orthogonal instruction set and supports up to six concurrent arithmetic and data-move operations in each instruction.

KW - CMOS process

KW - Digital signal processors

KW - Random access memory

KW - Read-write memory

KW - Registers

KW - Read only memory

KW - Data buses

KW - Hardware

KW - Pipelines

KW - Arithmetic

U2 - 10.1109/ISSCC.1986.1156982

DO - 10.1109/ISSCC.1986.1156982

M3 - Conference contribution

VL - XXIX

SP - 84

EP - 85

BT - 1986 IEEE International Solid-State Circuits Conference

PB - Institute of Electrical and Electronics Engineers

T2 - 1986 IEEE International Conference on Solid-State Circuits, ISSCC 1986

Y2 - 19 February 1986 through 21 February 1986

ER -

An 8MIPS CMOS digital signal processor

Abstract

Conference

Keywords

Access to Document

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Cite this