An 80dB-SNDR 98dB-SFDR Noise-Shaping SAR ADC with Duty-Cycled Amplifier and Digital-Predicted Mismatch Error Shaping

Hanyue Li; Yuting Shen; Haoming Xin; Eugenio Cantatore; Pieter Harpe

doi:10.1109/ESSCIRC53450.2021.9567748

An 80dB-SNDR 98dB-SFDR Noise-Shaping SAR ADC with Duty-Cycled Amplifier and Digital-Predicted Mismatch Error Shaping

Hanyue Li, Yuting Shen, Haoming Xin, Eugenio Cantatore, Pieter Harpe

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › Academic › peer-review

9 Citations (Scopus)

74 Downloads (Pure)

Abstract

This paper presents a low-power and high-linearity noise-shaping SAR ADC that employs a duty-cycled amplifier and a mismatch error shaping technique. The power-efficient duty-cycled amplifier with 18x gain and two passive integrators provide 2nd-order noise shaping to improve in-band noise attenuation. Mismatch error shaping with a two-level digital prediction scheme is used to 1st-order shape the capacitive DAC mismatch errors without sacrificing the input signal range. The proposed ADC is fabricated in 65 nm CMOS technology and achieves 80 dB peak SNDR and 98 dB peak SFDR in a 31.25 kHz bandwidth, leading to a Schreier FoM of 176.3 dB.

Original language	English
Title of host publication	ESSCIRC 2021 - IEEE 47th European Solid State Circuits Conference (ESSCIRC)
Publisher	Institute of Electrical and Electronics Engineers
Pages	387-390
Number of pages	4
ISBN (Electronic)	978-1-6654-3751-6
DOIs	https://doi.org/10.1109/ESSCIRC53450.2021.9567748
Publication status	Published - 26 Oct 2021
Event	47th IEEE European Solid State Circuits Conference, ESSCIRC 2021 - Virtual, Online, Grenoble, France Duration: 13 Sept 2021 → 22 Sept 2021 https://www.esscirc-essderc2021.org/

Conference

Conference	47th IEEE European Solid State Circuits Conference, ESSCIRC 2021
Country/Territory	France
City	Grenoble
Period	13/09/21 → 22/09/21
Internet address	https://www.esscirc-essderc2021.org/

Bibliographical note

Funding Information:
This work with project number 16594 is financed by the Dutch Research Council (NWO).

Funding

ACKNOWLEDGEMENTS This work with project number 16594 is financed by the Dutch Research Council (NWO).

Keywords

duty-cycled amplifier
high linearity
mismatch error shaping
noise-shaping SAR ADC

Access to Document

10.1109/ESSCIRC53450.2021.9567748

202109 ESSCIRC paperFinal author version , 1.57 MBLicence: Unspecified

Cite this

Li, H., Shen, Y., Xin, H., Cantatore, E., & Harpe, P. (2021). An 80dB-SNDR 98dB-SFDR Noise-Shaping SAR ADC with Duty-Cycled Amplifier and Digital-Predicted Mismatch Error Shaping. In ESSCIRC 2021 - IEEE 47th European Solid State Circuits Conference (ESSCIRC) (pp. 387-390). Article 9567748 Institute of Electrical and Electronics Engineers. https://doi.org/10.1109/ESSCIRC53450.2021.9567748

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title = "An 80dB-SNDR 98dB-SFDR Noise-Shaping SAR ADC with Duty-Cycled Amplifier and Digital-Predicted Mismatch Error Shaping",

abstract = "This paper presents a low-power and high-linearity noise-shaping SAR ADC that employs a duty-cycled amplifier and a mismatch error shaping technique. The power-efficient duty-cycled amplifier with 18x gain and two passive integrators provide 2nd-order noise shaping to improve in-band noise attenuation. Mismatch error shaping with a two-level digital prediction scheme is used to 1st-order shape the capacitive DAC mismatch errors without sacrificing the input signal range. The proposed ADC is fabricated in 65 nm CMOS technology and achieves 80 dB peak SNDR and 98 dB peak SFDR in a 31.25 kHz bandwidth, leading to a Schreier FoM of 176.3 dB. ",

keywords = "duty-cycled amplifier, high linearity, mismatch error shaping, noise-shaping SAR ADC",

author = "Hanyue Li and Yuting Shen and Haoming Xin and Eugenio Cantatore and Pieter Harpe",

note = "Funding Information: This work with project number 16594 is financed by the Dutch Research Council (NWO). ; 47th IEEE European Solid State Circuits Conference, ESSCIRC 2021 ; Conference date: 13-09-2021 Through 22-09-2021",

year = "2021",

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doi = "10.1109/ESSCIRC53450.2021.9567748",

language = "English",

pages = "387--390",

booktitle = "ESSCIRC 2021 - IEEE 47th European Solid State Circuits Conference (ESSCIRC)",

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Li, H, Shen, Y, Xin, H, Cantatore, E & Harpe, P 2021, An 80dB-SNDR 98dB-SFDR Noise-Shaping SAR ADC with Duty-Cycled Amplifier and Digital-Predicted Mismatch Error Shaping. in ESSCIRC 2021 - IEEE 47th European Solid State Circuits Conference (ESSCIRC)., 9567748, Institute of Electrical and Electronics Engineers, pp. 387-390, 47th IEEE European Solid State Circuits Conference, ESSCIRC 2021, Grenoble, France, 13/09/21. https://doi.org/10.1109/ESSCIRC53450.2021.9567748

An 80dB-SNDR 98dB-SFDR Noise-Shaping SAR ADC with Duty-Cycled Amplifier and Digital-Predicted Mismatch Error Shaping. / Li, Hanyue; Shen, Yuting; Xin, Haoming et al.
ESSCIRC 2021 - IEEE 47th European Solid State Circuits Conference (ESSCIRC). Institute of Electrical and Electronics Engineers, 2021. p. 387-390 9567748.

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › Academic › peer-review

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AU - Li, Hanyue

AU - Shen, Yuting

AU - Xin, Haoming

AU - Cantatore, Eugenio

AU - Harpe, Pieter

N1 - Funding Information: This work with project number 16594 is financed by the Dutch Research Council (NWO).

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N2 - This paper presents a low-power and high-linearity noise-shaping SAR ADC that employs a duty-cycled amplifier and a mismatch error shaping technique. The power-efficient duty-cycled amplifier with 18x gain and two passive integrators provide 2nd-order noise shaping to improve in-band noise attenuation. Mismatch error shaping with a two-level digital prediction scheme is used to 1st-order shape the capacitive DAC mismatch errors without sacrificing the input signal range. The proposed ADC is fabricated in 65 nm CMOS technology and achieves 80 dB peak SNDR and 98 dB peak SFDR in a 31.25 kHz bandwidth, leading to a Schreier FoM of 176.3 dB.

AB - This paper presents a low-power and high-linearity noise-shaping SAR ADC that employs a duty-cycled amplifier and a mismatch error shaping technique. The power-efficient duty-cycled amplifier with 18x gain and two passive integrators provide 2nd-order noise shaping to improve in-band noise attenuation. Mismatch error shaping with a two-level digital prediction scheme is used to 1st-order shape the capacitive DAC mismatch errors without sacrificing the input signal range. The proposed ADC is fabricated in 65 nm CMOS technology and achieves 80 dB peak SNDR and 98 dB peak SFDR in a 31.25 kHz bandwidth, leading to a Schreier FoM of 176.3 dB.

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KW - high linearity

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BT - ESSCIRC 2021 - IEEE 47th European Solid State Circuits Conference (ESSCIRC)

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ER -

An 80dB-SNDR 98dB-SFDR Noise-Shaping SAR ADC with Duty-Cycled Amplifier and Digital-Predicted Mismatch Error Shaping

Abstract

Conference

Bibliographical note

Funding

Keywords

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