An 80 MHz, 80 mW, 8-b CMOS folding A/D converter with distributed track-and-hold preprocessing

A.G.W. Venes; R.J. Plassche, van de

doi:10.1109/4.545804

An 80 MHz, 80 mW, 8-b CMOS folding A/D converter with distributed track-and-hold preprocessing

A.G.W. Venes, R.J. Plassche, van de

Integrated Circuits

Research output: Contribution to journal › Article › Academic › peer-review

130 Citations (Scopus)

Abstract

An analog-to-digital converter incorporating a distributed track-and-hold preprocessing combined with folding and interpolation techniques has been designed in CMOS technology. The presented extension of the well known folding concept has resulted in a 75 MHz maximum full-scale input signal frequency. A signal-to-noise ratio of 44 dB is obtained for this frequency. The 8-b A/D converter achieves a clock frequency of 80 MHz with a power dissipation of 80 mW from a 3.3 V supply voltage. The active chip area is 0.3 mm2 in 0.5-µm standard digital CMOS technology

Original language	English
Pages (from-to)	1846-1853
Number of pages	8
Journal	IEEE Journal of Solid-State Circuits
Volume	31
DOIs	https://doi.org/10.1109/4.545804
Publication status	Published - 1996

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title = "An 80 MHz, 80 mW, 8-b CMOS folding A/D converter with distributed track-and-hold preprocessing",

abstract = "An analog-to-digital converter incorporating a distributed track-and-hold preprocessing combined with folding and interpolation techniques has been designed in CMOS technology. The presented extension of the well known folding concept has resulted in a 75 MHz maximum full-scale input signal frequency. A signal-to-noise ratio of 44 dB is obtained for this frequency. The 8-b A/D converter achieves a clock frequency of 80 MHz with a power dissipation of 80 mW from a 3.3 V supply voltage. The active chip area is 0.3 mm2 in 0.5-µm standard digital CMOS technology",

author = "A.G.W. Venes and {Plassche, van de}, R.J.",

year = "1996",

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journal = "IEEE Journal of Solid-State Circuits",

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AU - Venes, A.G.W.

AU - Plassche, van de, R.J.

PY - 1996

Y1 - 1996

N2 - An analog-to-digital converter incorporating a distributed track-and-hold preprocessing combined with folding and interpolation techniques has been designed in CMOS technology. The presented extension of the well known folding concept has resulted in a 75 MHz maximum full-scale input signal frequency. A signal-to-noise ratio of 44 dB is obtained for this frequency. The 8-b A/D converter achieves a clock frequency of 80 MHz with a power dissipation of 80 mW from a 3.3 V supply voltage. The active chip area is 0.3 mm2 in 0.5-µm standard digital CMOS technology

AB - An analog-to-digital converter incorporating a distributed track-and-hold preprocessing combined with folding and interpolation techniques has been designed in CMOS technology. The presented extension of the well known folding concept has resulted in a 75 MHz maximum full-scale input signal frequency. A signal-to-noise ratio of 44 dB is obtained for this frequency. The 8-b A/D converter achieves a clock frequency of 80 MHz with a power dissipation of 80 mW from a 3.3 V supply voltage. The active chip area is 0.3 mm2 in 0.5-µm standard digital CMOS technology

U2 - 10.1109/4.545804

DO - 10.1109/4.545804

M3 - Article

VL - 31

SP - 1846

EP - 1853

JO - IEEE Journal of Solid-State Circuits

JF - IEEE Journal of Solid-State Circuits

SN - 0018-9200

ER -

An 80 MHz, 80 mW, 8-b CMOS folding A/D converter with distributed track-and-hold preprocessing

Abstract

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