Abstract
An analog-to-digital converter incorporating a distributed track-and-hold preprocessing combined with folding and interpolation techniques has been designed in CMOS technology. The presented extension of the well known folding concept has resulted in a 75 MHz maximum full-scale input signal frequency. A signal-to-noise ratio of 44 dB is obtained for this frequency. The 8-b A/D converter achieves a clock frequency of 80 MHz with a power dissipation of 80 mW from a 3.3 V supply voltage. The active chip area is 0.3 mm2 in 0.5-µm standard digital CMOS technology
Original language | English |
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Pages (from-to) | 1846-1853 |
Number of pages | 8 |
Journal | IEEE Journal of Solid-State Circuits |
Volume | 31 |
DOIs | |
Publication status | Published - 1996 |