An 8-bit 100-Mhz full-Nyquist analog-to-digital converter

Rudy J. Van De Plassche, Peter Baltus

Research output: Contribution to journalArticleAcademicpeer-review

76 Citations (Scopus)

Abstract

An 8-bit 100-MHz full-Nyquist analog-to-digital (A/D) converter using a folding and interpolation architecture is presented. In a folding system a multiple use of comparator stages is implemented. A reduction in the number of comparators, equal to the number of times the signal is folded, is obtained. However, every quantization level requires a folding stage, thus no reduction in input circuitry is found. Interpolation between the outputs of the folding stages generates additional folding signals without the need for input stages. A reduction in input circuitry equal to the number of interpolations is obtained. The folding and interpolation architecture leads to a compact, high-performance A/D converter system. In an oxide isolated bipolar process the 8-bit converter is implemented, requiring 800 mW from a single 5.2-V supply. Die size is 3.2 X 3.8 mm2. Up until now no real theoretical description of the speed limitation of flash-type A/D converters has existed. A high-level model describing distortion caused by timing errors is presented. Considering clock timing accuracies needed to obtain the speed requirement, this distortion is thought to be the main speed limitation. This model has been used to optimize the effective resolution bandwidth of the converter.

Original languageEnglish
Pages (from-to)1334-1344
Number of pages11
JournalIEEE Journal of Solid-State Circuits
Volume23
Issue number6
DOIs
Publication statusPublished - 1 Jan 1988
Externally publishedYes

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Digital to analog conversion
Interpolation
Clocks
Bandwidth
Oxides

Cite this

Van De Plassche, Rudy J. ; Baltus, Peter. / An 8-bit 100-Mhz full-Nyquist analog-to-digital converter. In: IEEE Journal of Solid-State Circuits. 1988 ; Vol. 23, No. 6. pp. 1334-1344.
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An 8-bit 100-Mhz full-Nyquist analog-to-digital converter. / Van De Plassche, Rudy J.; Baltus, Peter.

In: IEEE Journal of Solid-State Circuits, Vol. 23, No. 6, 01.01.1988, p. 1334-1344.

Research output: Contribution to journalArticleAcademicpeer-review

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