An 11b 1 GS/s ADC with parallel sampling architecture to enhance SNDR for multi-carrier signals

Y. Lin, K. Doris, E.J.G. Janssen, A. Zanikopoulos, A. Murroni, A. Weide, van der, J.A. Hegt, A.H.M. Roermund, van

Research output: Chapter in Book/Report/Conference proceedingConference contributionAcademicpeer-review

3 Citations (Scopus)

Abstract

This paper presents an 11b 1GS/s ADC with a parallel sampling architecture to enhance SNDR for broadband multi-carrier signals. It contains two 1GS/s 11b sub-ADCs each achieving > 54dB SNDR for input frequencies up to Nyquist frequency and state-of-the-art linearity performance. The SNDR of the ADC with the parallel sampling architecture is improved by 5dB compared to its sub-ADCs when digitizing multi-carrier signals with large crest factors. This improvement is achieved at less than half the cost in power and area compared to the conventional approach. The chip is implemented in 65nm LP CMOS and consumes in total 350mW at 1GS/s.
Original languageEnglish
Title of host publicationESSCIRC 2013 : proceedings of the 39th European solid‐state circuits conference : 16-20 September 2013, Bucharest
Pages121-124
DOIs
Publication statusPublished - 2013
Event39th European Solid-State Circuits Conference (ESSCIRC 2013) - JW Marriott Bucharest Grand Hotel, Bucharest, Romania
Duration: 16 Sep 201320 Sep 2013
Conference number: 39

Conference

Conference39th European Solid-State Circuits Conference (ESSCIRC 2013)
Abbreviated titleESSCIRC 2013
CountryRomania
CityBucharest
Period16/09/1320/09/13

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    Lin, Y., Doris, K., Janssen, E. J. G., Zanikopoulos, A., Murroni, A., Weide, van der, A., Hegt, J. A., & Roermund, van, A. H. M. (2013). An 11b 1 GS/s ADC with parallel sampling architecture to enhance SNDR for multi-carrier signals. In ESSCIRC 2013 : proceedings of the 39th European solid‐state circuits conference : 16-20 September 2013, Bucharest (pp. 121-124) https://doi.org/10.1109/ESSCIRC.2013.6649087