Finite field arithmetic over GF (2 to the nth) is particularly attractive for efficient implementations of elliptic curve cryptosystems in hardware. In this paper a new scalable multiplier architecture is proposed, combining the classical bit-serial method and Montgomery's modular multiplication algorithm. Using polynomial basis, this combined multiplier exhibits a double speed with an increase in hardware comlexity of only 50% compared to the classical type of multiplier. Special attention is given to the scalability and flexibility of the design. Performance data is given for an FPGA prototype implementation.
|Title of host publication||23rd Symposium on Information Theory in the Benelux|
|Editors||B. Macq, J.-J. Quisquater|
|Place of Publication||Brussels|
|Publisher||Werkgemeenschap voor Informatie- en Communicatietheorie (WIC)|
|Publication status||Published - 2002|