"Almost Montgomery" based multiplier in GF(2^n)

L. Batina; C.J.A. Jansen; G. Bruin - Muurling; S.B. Xu

"Almost Montgomery" based multiplier in GF(2^n)

L. Batina, C.J.A. Jansen, G. Bruin - Muurling, S.B. Xu

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › Academic › peer-review

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Abstract

Finite field arithmetic over GF (2 to the nth) is particularly attractive for efficient implementations of elliptic curve cryptosystems in hardware. In this paper a new scalable multiplier architecture is proposed, combining the classical bit-serial method and Montgomery's modular multiplication algorithm. Using polynomial basis, this combined multiplier exhibits a double speed with an increase in hardware comlexity of only 50% compared to the classical type of multiplier. Special attention is given to the scalability and flexibility of the design. Performance data is given for an FPGA prototype implementation.

Original language	English
Title of host publication	23rd Symposium on Information Theory in the Benelux
Editors	B. Macq, J.-J. Quisquater
Place of Publication	Brussels
Publisher	Werkgemeenschap voor Informatie- en Communicatietheorie (WIC)
Pages	61-68
ISBN (Print)	90-741048-16-0
Publication status	Published - 2002
Externally published	Yes

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Cite this

@inproceedings{f216a6ce8317427081ed301c4b354996,

title = "{"}Almost Montgomery{"} based multiplier in GF(2^n)",

abstract = "Finite field arithmetic over GF (2 to the nth) is particularly attractive for efficient implementations of elliptic curve cryptosystems in hardware. In this paper a new scalable multiplier architecture is proposed, combining the classical bit-serial method and Montgomery's modular multiplication algorithm. Using polynomial basis, this combined multiplier exhibits a double speed with an increase in hardware comlexity of only 50% compared to the classical type of multiplier. Special attention is given to the scalability and flexibility of the design. Performance data is given for an FPGA prototype implementation.",

author = "L. Batina and C.J.A. Jansen and {Bruin - Muurling}, G. and S.B. Xu",

year = "2002",

language = "English",

isbn = "90-741048-16-0",

pages = "61--68",

editor = "B. Macq and J.-J. Quisquater",

booktitle = "23rd Symposium on Information Theory in the Benelux",

publisher = "Werkgemeenschap voor Informatie- en Communicatietheorie (WIC)",

}

"Almost Montgomery" based multiplier in GF(2^n). / Batina, L.; Jansen, C.J.A.; Bruin - Muurling, G.; Xu, S.B.

23rd Symposium on Information Theory in the Benelux. ed. / B. Macq; J.-J. Quisquater. Brussels : Werkgemeenschap voor Informatie- en Communicatietheorie (WIC), 2002. p. 61-68.

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › Academic › peer-review

TY - GEN

T1 - "Almost Montgomery" based multiplier in GF(2^n)

AU - Batina, L.

AU - Jansen, C.J.A.

AU - Bruin - Muurling, G.

AU - Xu, S.B.

PY - 2002

Y1 - 2002

N2 - Finite field arithmetic over GF (2 to the nth) is particularly attractive for efficient implementations of elliptic curve cryptosystems in hardware. In this paper a new scalable multiplier architecture is proposed, combining the classical bit-serial method and Montgomery's modular multiplication algorithm. Using polynomial basis, this combined multiplier exhibits a double speed with an increase in hardware comlexity of only 50% compared to the classical type of multiplier. Special attention is given to the scalability and flexibility of the design. Performance data is given for an FPGA prototype implementation.

AB - Finite field arithmetic over GF (2 to the nth) is particularly attractive for efficient implementations of elliptic curve cryptosystems in hardware. In this paper a new scalable multiplier architecture is proposed, combining the classical bit-serial method and Montgomery's modular multiplication algorithm. Using polynomial basis, this combined multiplier exhibits a double speed with an increase in hardware comlexity of only 50% compared to the classical type of multiplier. Special attention is given to the scalability and flexibility of the design. Performance data is given for an FPGA prototype implementation.

M3 - Conference contribution

SN - 90-741048-16-0

SP - 61

EP - 68

BT - 23rd Symposium on Information Theory in the Benelux

A2 - Macq, B.

A2 - Quisquater, J.-J.

PB - Werkgemeenschap voor Informatie- en Communicatietheorie (WIC)

CY - Brussels

ER -