Abstract
Finite field arithmetic over GF (2 to the nth) is particularly attractive for efficient implementations of elliptic curve cryptosystems in hardware. In this paper a new scalable multiplier architecture is proposed, combining the classical bit-serial method and Montgomery's modular multiplication algorithm. Using polynomial basis, this combined multiplier exhibits a double speed with an increase in hardware comlexity of only 50% compared to the classical type of multiplier. Special attention is given to the scalability and flexibility of the design. Performance data is given for an FPGA prototype implementation.
Original language | English |
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Title of host publication | 23rd Symposium on Information Theory in the Benelux |
Editors | B. Macq, J.-J. Quisquater |
Place of Publication | Brussels |
Publisher | Werkgemeenschap voor Informatie- en Communicatietheorie (WIC) |
Pages | 61-68 |
ISBN (Print) | 90-741048-16-0 |
Publication status | Published - 2002 |
Externally published | Yes |