Algorithm/Architecture Co-design of the Generalized Sampling Theorem Based De-Interlacer.

A. Beric, G. Haan, de, R. Sethuraman, J. Meerbergen, van

Research output: Chapter in Book/Report/Conference proceedingConference contributionAcademicpeer-review

2 Citations (Scopus)

Abstract

De-interlacing is a major determinant of image quality in a modern display processing chain. The de-interlacing method based on the generalized sampling theorem (GST)applied to motion estimation and motion compensation provides the best de-interlacing results. With HDTV interlaced input material (1920*1080i), this method requires about 1000 GOPs and a communication bandwidth around 10 Gbytes/sec. We analyze and simplify the algorithm and propose a processing architecture. As a result, the operation count of the motion estimator decreases with a factor of 5.5 and the bandwidth to local pixel storage with a factor of 3.3 with only mild and acceptable quality loss. We present a task breakup and a suitable heterogeneous multi-processor architecture. The task break-up is such that the computational load of the processors is balanced and the flexibility of the architecture is preserved within the application domain. To cope with the large memory bandwidth requirements, we exploit locality of reference with multi-level scratchpad memories.
Original languageEnglish
Title of host publicationProceedings of the IEEE International Symposium on Circuits and Systems (ISCAS 2005) 23 - 26 May 2005, Kobe, Japan
Place of PublicationPiscataway, New Jersey, USA
PublisherInstitute of Electrical and Electronics Engineers
Pages2943-2946
ISBN (Print)0-7803-8834-8
Publication statusPublished - 2005
Event2005 IEEE International Symposium on Circuits and Systems (ISCAS 2005) - Kobe, Japan
Duration: 23 May 200526 May 2005

Conference

Conference2005 IEEE International Symposium on Circuits and Systems (ISCAS 2005)
Abbreviated titleISCAS 2005
CountryJapan
CityKobe
Period23/05/0526/05/05

Fingerprint

Sampling
Bandwidth
Data storage equipment
High definition television
Motion compensation
Motion estimation
Processing
Image quality
Pixels
Display devices
Communication

Cite this

Beric, A., Haan, de, G., Sethuraman, R., & Meerbergen, van, J. (2005). Algorithm/Architecture Co-design of the Generalized Sampling Theorem Based De-Interlacer. In Proceedings of the IEEE International Symposium on Circuits and Systems (ISCAS 2005) 23 - 26 May 2005, Kobe, Japan (pp. 2943-2946). Piscataway, New Jersey, USA: Institute of Electrical and Electronics Engineers.
Beric, A. ; Haan, de, G. ; Sethuraman, R. ; Meerbergen, van, J. / Algorithm/Architecture Co-design of the Generalized Sampling Theorem Based De-Interlacer. Proceedings of the IEEE International Symposium on Circuits and Systems (ISCAS 2005) 23 - 26 May 2005, Kobe, Japan. Piscataway, New Jersey, USA : Institute of Electrical and Electronics Engineers, 2005. pp. 2943-2946
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Beric, A, Haan, de, G, Sethuraman, R & Meerbergen, van, J 2005, Algorithm/Architecture Co-design of the Generalized Sampling Theorem Based De-Interlacer. in Proceedings of the IEEE International Symposium on Circuits and Systems (ISCAS 2005) 23 - 26 May 2005, Kobe, Japan. Institute of Electrical and Electronics Engineers, Piscataway, New Jersey, USA, pp. 2943-2946, 2005 IEEE International Symposium on Circuits and Systems (ISCAS 2005), Kobe, Japan, 23/05/05.

Algorithm/Architecture Co-design of the Generalized Sampling Theorem Based De-Interlacer. / Beric, A.; Haan, de, G.; Sethuraman, R.; Meerbergen, van, J.

Proceedings of the IEEE International Symposium on Circuits and Systems (ISCAS 2005) 23 - 26 May 2005, Kobe, Japan. Piscataway, New Jersey, USA : Institute of Electrical and Electronics Engineers, 2005. p. 2943-2946.

Research output: Chapter in Book/Report/Conference proceedingConference contributionAcademicpeer-review

TY - GEN

T1 - Algorithm/Architecture Co-design of the Generalized Sampling Theorem Based De-Interlacer.

AU - Beric, A.

AU - Haan, de, G.

AU - Sethuraman, R.

AU - Meerbergen, van, J.

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N2 - De-interlacing is a major determinant of image quality in a modern display processing chain. The de-interlacing method based on the generalized sampling theorem (GST)applied to motion estimation and motion compensation provides the best de-interlacing results. With HDTV interlaced input material (1920*1080i), this method requires about 1000 GOPs and a communication bandwidth around 10 Gbytes/sec. We analyze and simplify the algorithm and propose a processing architecture. As a result, the operation count of the motion estimator decreases with a factor of 5.5 and the bandwidth to local pixel storage with a factor of 3.3 with only mild and acceptable quality loss. We present a task breakup and a suitable heterogeneous multi-processor architecture. The task break-up is such that the computational load of the processors is balanced and the flexibility of the architecture is preserved within the application domain. To cope with the large memory bandwidth requirements, we exploit locality of reference with multi-level scratchpad memories.

AB - De-interlacing is a major determinant of image quality in a modern display processing chain. The de-interlacing method based on the generalized sampling theorem (GST)applied to motion estimation and motion compensation provides the best de-interlacing results. With HDTV interlaced input material (1920*1080i), this method requires about 1000 GOPs and a communication bandwidth around 10 Gbytes/sec. We analyze and simplify the algorithm and propose a processing architecture. As a result, the operation count of the motion estimator decreases with a factor of 5.5 and the bandwidth to local pixel storage with a factor of 3.3 with only mild and acceptable quality loss. We present a task breakup and a suitable heterogeneous multi-processor architecture. The task break-up is such that the computational load of the processors is balanced and the flexibility of the architecture is preserved within the application domain. To cope with the large memory bandwidth requirements, we exploit locality of reference with multi-level scratchpad memories.

M3 - Conference contribution

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BT - Proceedings of the IEEE International Symposium on Circuits and Systems (ISCAS 2005) 23 - 26 May 2005, Kobe, Japan

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Beric A, Haan, de G, Sethuraman R, Meerbergen, van J. Algorithm/Architecture Co-design of the Generalized Sampling Theorem Based De-Interlacer. In Proceedings of the IEEE International Symposium on Circuits and Systems (ISCAS 2005) 23 - 26 May 2005, Kobe, Japan. Piscataway, New Jersey, USA: Institute of Electrical and Electronics Engineers. 2005. p. 2943-2946