These proceedings describe processing, materials and equipment for CMOS front-end integration including gate stack, source/drain and channel engineering. Topics: strained Si/SiGe and Si/SiGe on insulator; high-mobility channels including III-Vzs, etc.; nanowires and carbon nanotubes; high-k dielectrics, metal and FUSI gate electrodes; doping/annealing for ultra-shallow junctions; low-resistivity contacts; advanced deposition (e.g. ALD, CVD, MBE), RTP, UV, plasma and laser-assisted processes.
|Place of Publication||Pennington, N.J.|
|Number of pages||412|
|ISBN (Print)||978-1-56677-791-9, 978-1-60768-141-0|
|Publication status||Published - 2010|
Bibliographical noteVancouver, Canada, April 26-27, 2010, held as a part of the 217th meeting of the Electrochemical Society (ECS)
Gusev, E. P., Iwai, H., Kwong, D-L., Öztürk, M., Roozeboom, F., Timans, P. J., & Narayanan, V. (Eds.) (2010). Advanced gate stack, source/drain and channel engineering for Si-based CMOS 6 : new materials, processes and equipment. (ECS transactions; Vol. 28, No. 1). Electrochemical Society. http://ecst.ecsdl.org/content/28/1