Accelerating time domain simulations of PLLs

G. De Luca; W.H.A. Schilders; P. Bolcato; R. Larcheveque; J. Rommes

doi:10.1109/SaPIW.2016.7496299

Accelerating time domain simulations of PLLs

G. De Luca, W.H.A. Schilders, P. Bolcato, R. Larcheveque, J. Rommes

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › Academic › peer-review

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Abstract

We present a method to speed up noise-free and noisy time domain simulations of industrial integer-N PLLs, while extracting the main factors of interest which circuit designers are interested in, i.e., locking time, power consumption, phase noise and jitter, within desirable error levels. The procedure is based on oscillator's sensitivity analysis and on the creation of a phase macromodel for it and the loop divider.

Original language	English
Title of host publication	2016 IEEE 20th Workshop on Signal and Power Integrity, SPI 2016 - Proceedings
Publisher	Institute of Electrical and Electronics Engineers
Number of pages	4
ISBN (Electronic)	9781509003495
DOIs	https://doi.org/10.1109/SaPIW.2016.7496299
Publication status	Published - 20 Jun 2016
Event	20th IEEE Workshop on Signal and Power Integrity (SPI 2016), 8-11 May 2016, Turin, Italy - Turin, Italy Duration: 8 May 2016 → 11 May 2016 http://www.spi2016.org/

Conference

Conference	20th IEEE Workshop on Signal and Power Integrity (SPI 2016), 8-11 May 2016, Turin, Italy
Abbreviated title	SPI 2016
Country/Territory	Italy
City	Turin
Period	8/05/16 → 11/05/16
Internet address	http://www.spi2016.org/

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10.1109/SaPIW.2016.7496299

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title = "Accelerating time domain simulations of PLLs",

abstract = "We present a method to speed up noise-free and noisy time domain simulations of industrial integer-N PLLs, while extracting the main factors of interest which circuit designers are interested in, i.e., locking time, power consumption, phase noise and jitter, within desirable error levels. The procedure is based on oscillator's sensitivity analysis and on the creation of a phase macromodel for it and the loop divider.",

author = "{De Luca}, G. and W.H.A. Schilders and P. Bolcato and R. Larcheveque and J. Rommes",

year = "2016",

month = jun,

day = "20",

doi = "10.1109/SaPIW.2016.7496299",

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booktitle = "2016 IEEE 20th Workshop on Signal and Power Integrity, SPI 2016 - Proceedings",

publisher = "Institute of Electrical and Electronics Engineers",

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note = "20th IEEE Workshop on Signal and Power Integrity (SPI 2016), 8-11 May 2016, Turin, Italy, SPI 2016 ; Conference date: 08-05-2016 Through 11-05-2016",

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De Luca, G, Schilders, WHA, Bolcato, P, Larcheveque, R & Rommes, J 2016, Accelerating time domain simulations of PLLs. in 2016 IEEE 20th Workshop on Signal and Power Integrity, SPI 2016 - Proceedings., 7496299, Institute of Electrical and Electronics Engineers, 20th IEEE Workshop on Signal and Power Integrity (SPI 2016), 8-11 May 2016, Turin, Italy, Turin, Italy, 8/05/16. https://doi.org/10.1109/SaPIW.2016.7496299

TY - GEN

T1 - Accelerating time domain simulations of PLLs

AU - De Luca, G.

AU - Schilders, W.H.A.

AU - Bolcato, P.

AU - Larcheveque, R.

AU - Rommes, J.

PY - 2016/6/20

Y1 - 2016/6/20

N2 - We present a method to speed up noise-free and noisy time domain simulations of industrial integer-N PLLs, while extracting the main factors of interest which circuit designers are interested in, i.e., locking time, power consumption, phase noise and jitter, within desirable error levels. The procedure is based on oscillator's sensitivity analysis and on the creation of a phase macromodel for it and the loop divider.

AB - We present a method to speed up noise-free and noisy time domain simulations of industrial integer-N PLLs, while extracting the main factors of interest which circuit designers are interested in, i.e., locking time, power consumption, phase noise and jitter, within desirable error levels. The procedure is based on oscillator's sensitivity analysis and on the creation of a phase macromodel for it and the loop divider.

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U2 - 10.1109/SaPIW.2016.7496299

DO - 10.1109/SaPIW.2016.7496299

M3 - Conference contribution

AN - SCOPUS:84980395704

BT - 2016 IEEE 20th Workshop on Signal and Power Integrity, SPI 2016 - Proceedings

PB - Institute of Electrical and Electronics Engineers

T2 - 20th IEEE Workshop on Signal and Power Integrity (SPI 2016), 8-11 May 2016, Turin, Italy

Y2 - 8 May 2016 through 11 May 2016

ER -

Accelerating time domain simulations of PLLs

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