Accelerating time domain simulations of PLLs

G. De Luca, W.H.A. Schilders, P. Bolcato, R. Larcheveque, J. Rommes

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Abstract

We present a method to speed up noise-free and noisy time domain simulations of industrial integer-N PLLs, while extracting the main factors of interest which circuit designers are interested in, i.e., locking time, power consumption, phase noise and jitter, within desirable error levels. The procedure is based on oscillator's sensitivity analysis and on the creation of a phase macromodel for it and the loop divider.

Original languageEnglish
Title of host publication2016 IEEE 20th Workshop on Signal and Power Integrity, SPI 2016 - Proceedings
PublisherInstitute of Electrical and Electronics Engineers
Number of pages4
ISBN (Electronic)9781509003495
DOIs
Publication statusPublished - 20 Jun 2016
Event20th IEEE Workshop on Signal and Power Integrity (SPI 2016), 8-11 May 2016, Turin, Italy - Turin, Italy
Duration: 8 May 201611 May 2016
http://www.spi2016.org/

Conference

Conference20th IEEE Workshop on Signal and Power Integrity (SPI 2016), 8-11 May 2016, Turin, Italy
Abbreviated titleSPI 2016
CountryItaly
CityTurin
Period8/05/1611/05/16
Internet address

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