Abstract
This paper presents an approach advocating abstract clocks to represent data-intensive applications executed on multiprocessor systems-on-chip (MPSoCs) for facilitating the exploration of large design spaces. By using abstract clocks, the advocated method characterizes applications defined by multiple loop nests, as well as, useful loop transformations that contribute to an efficient application execution. It combines the advantages of optimizations provided by loop transformations and the precision of information on scheduling captured by the abstract clocks. As a result, it favors a rapid, and yet accurate design space exploration (DSE) of data-intensive systems.
Original language | English |
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Title of host publication | Proceedings of the 2012 IEEE 10th International Symposium on Parallel and Distributed Processing with Applications (ISPA), 10-13 July 2012, Leganés, Madrid |
Place of Publication | Piscataway |
Publisher | Institute of Electrical and Electronics Engineers |
Pages | 729-736 |
DOIs | |
Publication status | Published - 2012 |
Event | 10th International Symposium on Parallel and Distributed Processing with Applications (ISPA 2012) - Leganes, Spain Duration: 10 Jul 2012 → 13 Jul 2012 Conference number: 10 http://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=6280412 |
Conference
Conference | 10th International Symposium on Parallel and Distributed Processing with Applications (ISPA 2012) |
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Abbreviated title | ISPA 2012 |
Country/Territory | Spain |
City | Leganes |
Period | 10/07/12 → 13/07/12 |
Internet address |