A106nW 10 b 80 kS/s SAR ADC with duty-cycled reference generation in 65 nm CMOS

M. Liu, Kevin M.P. Pelzers, A.R. van Dommele, A.H.M. van Roermund, P.J.A. Harpe

Research output: Contribution to journalArticleAcademicpeer-review

22 Citations (Scopus)
53 Downloads (Pure)


This paper presents a 10 b 80 kS/s SAR ADC with low-power duty-cycled reference generation. It generates a stable reference voltage on chip for the SAR ADC and imparts very good immunity against power supply interference to the ADC. A 0.62 V-VDD 25 nW CMOS reference voltage generator (RVG) is presented, which has only ±1.5% variation over process corners. A duty-cycling technique is applied to enable 10% duty-cycling of the RVG, resulting in negligible power consumption of the RVG compared to that of the ADC. Furthermore, a bi-directional dynamic preamplifier is adopted in the SAR ADC, which consumes about half the power compared with a regular dynamic structure and maintains noise and gain performance. Compared with prior-art low-power ADCs, this work is the first to integrate the reference generation and include it in the power consumption while maintaining a competitive 2.4 fJ/conversion-step FoM. The chip is fabricated in 65 nm CMOS technology.
Original languageEnglish
Pages (from-to)2435-2445
JournalIEEE Journal of Solid-State Circuits
Issue number10
Publication statusPublished - Oct 2016


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