A yield centric statistical design method for optimization of the SRAM active column

T.S. Doorn, J.A. Croon, E.J.W. Maten, ter, A. Di Bucchianico

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Abstract

For robust design of SRAM memories, it is not sufficient to guarantee good statistical margins on the SRAM cell parameters. The sense amplifier needs sufficient input signal before it can reliably sense the data, while the SRAM cell requires sufficient time to develop that input signal. This paper presents a new statistical method that allows optimization of the access time of an SRAM memory, while guaranteeing a yield target set by the designer. Using this method, the access time of a high performance advanced CMOS SRAM has been improved 6%, while simultaneously reducing the sense amplifier size
Original languageEnglish
Title of host publicationProceedings of the 35th European Solid-State Circuits Conference (ESSCIRC 2009, Athens, Greece, September 14-18, 2009)
Place of PublicationPiscataway, NJ
PublisherInstitute of Electrical and Electronics Engineers
Pages352-355
ISBN (Print)978-1-4244-4354-3
DOIs
Publication statusPublished - 2009

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    Doorn, T. S., Croon, J. A., Maten, ter, E. J. W., & Di Bucchianico, A. (2009). A yield centric statistical design method for optimization of the SRAM active column. In Proceedings of the 35th European Solid-State Circuits Conference (ESSCIRC 2009, Athens, Greece, September 14-18, 2009) (pp. 352-355). Institute of Electrical and Electronics Engineers. https://doi.org/10.1109/ESSCIRC.2009.5325954