A wideband envelope detector with low ripple and high detection speed

K. Ying; H. Gao; X. Min; D. Milosevic; P. Baltus

doi:10.1109/ISCAS.2018.8351246

A wideband envelope detector with low ripple and high detection speed

K. Ying, H. Gao, X. Min, D. Milosevic, P. Baltus

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › Academic › peer-review

3 Citations (Scopus)

2 Downloads (Pure)

Abstract

In this paper, a new envelope detector design in a 40nm CMOS technology is presented. The design employs quadrature signal generation and 2^nd harmonic cancellation to reduce output ripple while achieving high detection speed at the same time. The envelope detector operates from 500MHz to 6GHz with a detection speed of 250 MHz. It achieves less than 2% ripple, 0.64 ns delay and consumes 76.9 uW. With the achieved results, it is suitable for use in a nonlinear interference suppression receiver, enabling more than 25 dB of suppression.

Original language	English
Title of host publication	2018 IEEE International Symposium on Circuits and Systems, ISCAS 2018 - Proceedings
Publisher	Institute of Electrical and Electronics Engineers
Pages	1-5
Number of pages	5
Volume	2018-May
ISBN (Electronic)	9781538648810
DOIs	https://doi.org/10.1109/ISCAS.2018.8351246
Publication status	Published - 26 Apr 2018
Event	2018 IEEE International Symposium on Circuits and Systems (ISCAS 2018) - Florence Conference Center, Florence, Italy Duration: 27 May 2018 → 30 May 2018 https://ieeexplore.ieee.org/xpl/mostRecentIssue.jsp?punumber=8334884

Conference

Conference	2018 IEEE International Symposium on Circuits and Systems (ISCAS 2018)
Abbreviated title	ISCAS 2018
Country/Territory	Italy
City	Florence
Period	27/05/18 → 30/05/18
Internet address	https://ieeexplore.ieee.org/xpl/mostRecentIssue.jsp?punumber=8334884

Keywords

envelope detector
harmonic rejection
interference suppression
quadrature generation

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10.1109/ISCAS.2018.8351246

Cite this

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title = "A wideband envelope detector with low ripple and high detection speed",

abstract = "In this paper, a new envelope detector design in a 40nm CMOS technology is presented. The design employs quadrature signal generation and 2nd harmonic cancellation to reduce output ripple while achieving high detection speed at the same time. The envelope detector operates from 500MHz to 6GHz with a detection speed of 250 MHz. It achieves less than 2% ripple, 0.64 ns delay and consumes 76.9 uW. With the achieved results, it is suitable for use in a nonlinear interference suppression receiver, enabling more than 25 dB of suppression.",

keywords = "envelope detector, harmonic rejection, interference suppression, quadrature generation",

author = "K. Ying and H. Gao and X. Min and D. Milosevic and P. Baltus",

year = "2018",

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doi = "10.1109/ISCAS.2018.8351246",

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note = "2018 IEEE International Symposium on Circuits and Systems (ISCAS 2018), ISCAS 2018 ; Conference date: 27-05-2018 Through 30-05-2018",

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Ying, K, Gao, H, Min, X, Milosevic, D & Baltus, P 2018, A wideband envelope detector with low ripple and high detection speed. in 2018 IEEE International Symposium on Circuits and Systems, ISCAS 2018 - Proceedings. vol. 2018-May, 8351246, Institute of Electrical and Electronics Engineers, pp. 1-5, 2018 IEEE International Symposium on Circuits and Systems (ISCAS 2018), Florence, Italy, 27/05/18. https://doi.org/10.1109/ISCAS.2018.8351246

A wideband envelope detector with low ripple and high detection speed. / Ying, K.; Gao, H.; Min, X. et al.
2018 IEEE International Symposium on Circuits and Systems, ISCAS 2018 - Proceedings. Vol. 2018-May Institute of Electrical and Electronics Engineers, 2018. p. 1-5 8351246.

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › Academic › peer-review

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T1 - A wideband envelope detector with low ripple and high detection speed

AU - Ying, K.

AU - Gao, H.

AU - Min, X.

AU - Milosevic, D.

AU - Baltus, P.

PY - 2018/4/26

Y1 - 2018/4/26

N2 - In this paper, a new envelope detector design in a 40nm CMOS technology is presented. The design employs quadrature signal generation and 2nd harmonic cancellation to reduce output ripple while achieving high detection speed at the same time. The envelope detector operates from 500MHz to 6GHz with a detection speed of 250 MHz. It achieves less than 2% ripple, 0.64 ns delay and consumes 76.9 uW. With the achieved results, it is suitable for use in a nonlinear interference suppression receiver, enabling more than 25 dB of suppression.

AB - In this paper, a new envelope detector design in a 40nm CMOS technology is presented. The design employs quadrature signal generation and 2nd harmonic cancellation to reduce output ripple while achieving high detection speed at the same time. The envelope detector operates from 500MHz to 6GHz with a detection speed of 250 MHz. It achieves less than 2% ripple, 0.64 ns delay and consumes 76.9 uW. With the achieved results, it is suitable for use in a nonlinear interference suppression receiver, enabling more than 25 dB of suppression.

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KW - harmonic rejection

KW - interference suppression

KW - quadrature generation

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M3 - Conference contribution

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BT - 2018 IEEE International Symposium on Circuits and Systems, ISCAS 2018 - Proceedings

PB - Institute of Electrical and Electronics Engineers

T2 - 2018 IEEE International Symposium on Circuits and Systems (ISCAS 2018)

Y2 - 27 May 2018 through 30 May 2018

ER -

A wideband envelope detector with low ripple and high detection speed

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Keywords

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