Abstract
An IC for 100-Hz television has been realized implementing motion estimation and compensation algorithms for high-quality upconversion and a judder-free motion portrayal of movie material. The four embedded video signal processors on this IC provide a processing power of 10 giga-operation per second (GOPS). Their architecture was generated from an algorithm description using behavioral synthesis. The required 25-Gb/s memory bandwidth was realized by embedding 24 single/dual port SRAM/DRAM instances. The test approach includes full scan, boundary scan, functional testing, built-in-self-test, and IDDq-test. The so-called "Natural Motion" feature implemented by this IC was demonstrated at the IFA '95 and received the European Video Innovation Award 95-96.
| Original language | English |
|---|---|
| Pages (from-to) | 1762-1768 |
| Number of pages | 7 |
| Journal | IEEE Journal of Solid-State Circuits |
| Volume | 31 |
| Issue number | 11 |
| Publication status | Published - 1 Nov 1996 |
| Externally published | Yes |