Purpose – To simulate large parasitic resistive networks, one must reduce the size of the circuit models through methods that are accurate and preserve terminal connectivity and network sparsity. The purpose here is to present such a method, which exploits concepts from graph theory in a systematic fashion. Design/methodology/approach – The model order reduction problem is formulated for parasitic resistive networks through graph theory concepts and algorithms are presented based on the notion of vertex cut in order to reduce the size of electronic circuit models. Four variants of the basic method are proposed and their respective merits discussed. Findings – The algorithms proposed enable the production of networks that are significantly smaller than those produced by earlier methods, in particular the method described in the report by Lenaers entitled "Model order reduction for large resistive networks". The reduction in the number of resistors achieved through the algorithms is even more pronounced in the case of large networks. Originality/value – The paper seems to be the first to make a systematic use of vertex cuts in order to reduce a parasitic resistive network.
|Journal||COMPEL: The International Journal for Computation and Mathematics in Electrical and Electronic Engineering|
|Publication status||Published - 2012|