TY - JOUR
T1 - A unified approach to mapping and routing on a network-on-chip for both best-effort and guaranteed service traffic
AU - Hansson, M.A.
AU - Goossens, K.G.W.
AU - Radulescu, A.
PY - 2007
Y1 - 2007
N2 - One of the key steps in Network-on-Chip-based design is spatial mapping of cores and routing of the communication between those cores. Known solutions to the mapping and routing problems first map cores onto a topology and then route communication, using separate and possibly conflicting objective functions. In this paper, we present a unified single-objective algorithm, called Unified MApping, Routing, and Slot allocation (UMARS+). As the main contribution, we show how to couple path selection, mapping of cores, and channel time-slot allocation to minimize the network required to meet the constraints of the application. The time-complexity of UMARS+ is low and experimental results indicate a run-time only 20% higher than that of path selection alone. We apply the algorithm to an MPEG decoder System-on-Chip, reducing area by 33%, power dissipation by 35%, and worst-case latency by a factor four over a traditional waterfall approach. U7 - Cited By (since 1996): 6 U7 - Export Date: 5 February 2010 U7 - Source: Scopus U7 - Art. No.: 68432
AB - One of the key steps in Network-on-Chip-based design is spatial mapping of cores and routing of the communication between those cores. Known solutions to the mapping and routing problems first map cores onto a topology and then route communication, using separate and possibly conflicting objective functions. In this paper, we present a unified single-objective algorithm, called Unified MApping, Routing, and Slot allocation (UMARS+). As the main contribution, we show how to couple path selection, mapping of cores, and channel time-slot allocation to minimize the network required to meet the constraints of the application. The time-complexity of UMARS+ is low and experimental results indicate a run-time only 20% higher than that of path selection alone. We apply the algorithm to an MPEG decoder System-on-Chip, reducing area by 33%, power dissipation by 35%, and worst-case latency by a factor four over a traditional waterfall approach. U7 - Cited By (since 1996): 6 U7 - Export Date: 5 February 2010 U7 - Source: Scopus U7 - Art. No.: 68432
U2 - 10.1155/2007/68432
DO - 10.1155/2007/68432
M3 - Article
SN - 1065-514X
VL - 2007
JO - VLSI Design
JF - VLSI Design
ER -