A unified approach to constrained mapping and routing on network-on-chip architectures

M.A. Hansson; K.G.W. Goossens; A. Radulescu

doi:10.1145/1084834.1084857

A unified approach to constrained mapping and routing on network-on-chip architectures

M.A. Hansson, K.G.W. Goossens, A. Radulescu

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › Academic › peer-review

123 Citations (Scopus)

2 Downloads (Pure)

Abstract

One of the key steps in Network-on-Chip (NoC) based design is spatial mapping of cores and routing of the communication between those cores. Known solutions to the mapping and routing problem first map cores onto a topology and then route communication, using separated and possibly conflicting objective functions. In this paper we present a unified single-objective algorithm, called Unified MApping, Routing and Slot allocation (UMARS). As the main contribution we show how to couple path selection, mapping of cores and TDMA time-slot allocation such that the network required to meet the constraints of the application is minimized. The time-complexity of UMARS is low and experimental results indicate a run-time only 20% higher than that of path selection alone. We apply the algorithm to an MPEG decoder System-on-Chip (SoC), reducing area by 33%, power by 35% and worst-case latency by a factor four over a traditional multi-step approach. Copyright 2005 ACM.

Original language	English
Title of host publication	CODES+ISSS 2005 : International Conference on Hardware/Software Codesign and System Synthesis ; September 18 - 21, 2005, Jersey City, New Jersey, USA
Place of Publication	New York
Publisher	Association for Computing Machinery, Inc.
Pages	75-80
ISBN (Print)	1-59593-161-9
DOIs	https://doi.org/10.1145/1084834.1084857
Publication status	Published - 2005
Event	3rd IEEE/ACM/IFIP International Conference on Hardware/Software Codesign and Systems Synthesis (CODES+ISSS 2005) - New Jersey, United States Duration: 18 Sept 2005 → 21 Sept 2005 Conference number: 3

Conference

Conference	3rd IEEE/ACM/IFIP International Conference on Hardware/Software Codesign and Systems Synthesis (CODES+ISSS 2005)
Abbreviated title	CODES+ISSS 2005
Country/Territory	United States
City	New Jersey
Period	18/09/05 → 21/09/05

Access to Document

10.1145/1084834.1084857

Best Paper Award at the Int'l Conf. on Hardware/Software Codesign and System Synthesis (CODES+ISSS)
Goossens, K. G. W. (Recipient), 2005
Prize: Other › Career, activity or publication related prizes (lifetime, best paper, poster etc.) › Scientific

Cite this

Hansson, M. A., Goossens, K. G. W., & Radulescu, A. (2005). A unified approach to constrained mapping and routing on network-on-chip architectures. In CODES+ISSS 2005 : International Conference on Hardware/Software Codesign and System Synthesis ; September 18 - 21, 2005, Jersey City, New Jersey, USA (pp. 75-80). Association for Computing Machinery, Inc.. https://doi.org/10.1145/1084834.1084857

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abstract = "One of the key steps in Network-on-Chip (NoC) based design is spatial mapping of cores and routing of the communication between those cores. Known solutions to the mapping and routing problem first map cores onto a topology and then route communication, using separated and possibly conflicting objective functions. In this paper we present a unified single-objective algorithm, called Unified MApping, Routing and Slot allocation (UMARS). As the main contribution we show how to couple path selection, mapping of cores and TDMA time-slot allocation such that the network required to meet the constraints of the application is minimized. The time-complexity of UMARS is low and experimental results indicate a run-time only 20% higher than that of path selection alone. We apply the algorithm to an MPEG decoder System-on-Chip (SoC), reducing area by 33%, power by 35% and worst-case latency by a factor four over a traditional multi-step approach. Copyright 2005 ACM.",

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publisher = "Association for Computing Machinery, Inc.",

address = "United States",

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Hansson, MA, Goossens, KGW & Radulescu, A 2005, A unified approach to constrained mapping and routing on network-on-chip architectures. in CODES+ISSS 2005 : International Conference on Hardware/Software Codesign and System Synthesis ; September 18 - 21, 2005, Jersey City, New Jersey, USA. Association for Computing Machinery, Inc., New York, pp. 75-80, 3rd IEEE/ACM/IFIP International Conference on Hardware/Software Codesign and Systems Synthesis (CODES+ISSS 2005), New Jersey, New Jersey, United States, 18/09/05. https://doi.org/10.1145/1084834.1084857

A unified approach to constrained mapping and routing on network-on-chip architectures. / Hansson, M.A.; Goossens, K.G.W.; Radulescu, A.
CODES+ISSS 2005 : International Conference on Hardware/Software Codesign and System Synthesis ; September 18 - 21, 2005, Jersey City, New Jersey, USA. New York: Association for Computing Machinery, Inc., 2005. p. 75-80.

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › Academic › peer-review

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AU - Hansson, M.A.

AU - Goossens, K.G.W.

AU - Radulescu, A.

N1 - Conference code: 3

PY - 2005

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N2 - One of the key steps in Network-on-Chip (NoC) based design is spatial mapping of cores and routing of the communication between those cores. Known solutions to the mapping and routing problem first map cores onto a topology and then route communication, using separated and possibly conflicting objective functions. In this paper we present a unified single-objective algorithm, called Unified MApping, Routing and Slot allocation (UMARS). As the main contribution we show how to couple path selection, mapping of cores and TDMA time-slot allocation such that the network required to meet the constraints of the application is minimized. The time-complexity of UMARS is low and experimental results indicate a run-time only 20% higher than that of path selection alone. We apply the algorithm to an MPEG decoder System-on-Chip (SoC), reducing area by 33%, power by 35% and worst-case latency by a factor four over a traditional multi-step approach. Copyright 2005 ACM.

AB - One of the key steps in Network-on-Chip (NoC) based design is spatial mapping of cores and routing of the communication between those cores. Known solutions to the mapping and routing problem first map cores onto a topology and then route communication, using separated and possibly conflicting objective functions. In this paper we present a unified single-objective algorithm, called Unified MApping, Routing and Slot allocation (UMARS). As the main contribution we show how to couple path selection, mapping of cores and TDMA time-slot allocation such that the network required to meet the constraints of the application is minimized. The time-complexity of UMARS is low and experimental results indicate a run-time only 20% higher than that of path selection alone. We apply the algorithm to an MPEG decoder System-on-Chip (SoC), reducing area by 33%, power by 35% and worst-case latency by a factor four over a traditional multi-step approach. Copyright 2005 ACM.

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DO - 10.1145/1084834.1084857

M3 - Conference contribution

SN - 1-59593-161-9

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BT - CODES+ISSS 2005 : International Conference on Hardware/Software Codesign and System Synthesis ; September 18 - 21, 2005, Jersey City, New Jersey, USA

PB - Association for Computing Machinery, Inc.

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T2 - 3rd IEEE/ACM/IFIP International Conference on Hardware/Software Codesign and Systems Synthesis (CODES+ISSS 2005)

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Hansson MA, Goossens KGW, Radulescu A. A unified approach to constrained mapping and routing on network-on-chip architectures. In CODES+ISSS 2005 : International Conference on Hardware/Software Codesign and System Synthesis ; September 18 - 21, 2005, Jersey City, New Jersey, USA. New York: Association for Computing Machinery, Inc. 2005. p. 75-80 doi: 10.1145/1084834.1084857

A unified approach to constrained mapping and routing on network-on-chip architectures

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Prizes

Best Paper Award at the Int'l Conf. on Hardware/Software Codesign and System Synthesis (CODES+ISSS)

Cite this