A transformation of SDL specifications : a step towards the verification

N. Ioustinova, N. Sidorova

Research output: Chapter in Book/Report/Conference proceedingConference contributionAcademicpeer-review

1 Citation (Scopus)

Abstract

Industrial-size specifications/models (whose state space is often infinite) can not be model checked in a direct way— a verification model of a system is model checked instead. Program transformation is a way to build a finite-state verification model that can be submitted to a model checker. Abstraction is another technique that can be used for the same purpose. This paper presents a transformation of SDL timers aimed at the reduction of the infinite domain of timer values to a finite one with preserving the behaviour of a system. A timer abstraction is proposed to further reduce the state space. We discuss the ideas behind these transformations and argue their correctness.
Original languageEnglish
Title of host publicationPerspectives of System Informatics (4th International Andrei Ershov Memorial Conference, PSI 2001 Akademgorodok, Novosibirsk, Russia, July 2–6, 2001. Revised Papers)
EditorsD. Bjorner, M. Broy, A. Zamulin
Place of PublicationBerlin
PublisherSpringer
Pages64-78
ISBN (Print)3-540-43075-X
DOIs
Publication statusPublished - 2001
Eventconference; 4th International Andrei Ershov Memorial Conference -
Duration: 1 Jan 2001 → …

Publication series

NameLecture Notes in Computer Science
Volume2244
ISSN (Print)0302-9743

Conference

Conferenceconference; 4th International Andrei Ershov Memorial Conference
Period1/01/01 → …
Other4th International Andrei Ershov Memorial Conference

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