A test time reduction algorithm for test architecture design for core-based system chips

S.K. Goel, E.J. Marinissen

Research output: Contribution to journalArticleAcademicpeer-review

4 Citations (Scopus)

Fingerprint

Dive into the research topics of 'A test time reduction algorithm for test architecture design for core-based system chips'. Together they form a unique fingerprint.

Engineering & Materials Science