A test time reduction algorithm for test architecture design for core-based system chips

S.K. Goel, E.J. Marinissen

Research output: Contribution to journalArticleAcademicpeer-review

3 Citations (Scopus)


This paper deals with the design of SOC test architectures which are efficient with respect to required ATE vector memory depth and test application time. We advocate the usage of a TestRail Architecture, as this architecture, unlike others, allows not only for efficient core-internal testing, but also for efficient testing of the circuitry external to the cores. We present a novel heuristic algorithm that effectively optimizes the TestRail Architecture for a given SOC by efficiently determining the number of TestRails and their widths, the assignment of cores to the TestRails, and the wrapper design per core. Experimental results for four benchmark SOCs show that, compared to previously published algorithms, we obtain comparable or better test times at negligible compute time.
Original languageEnglish
Pages (from-to)425-435
JournalJournal of Electronic Testing : Theory and Applications
Issue number4
Publication statusPublished - Aug 2003
Externally publishedYes


  • SOC-test
  • TAM and wrapper design
  • test scheduling

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