Abstract
This paper presents a latched comparator designed in a double-gate p-type-only organic thin film transistors (OTFTs) technology. The circuit is tailored to take the maximum advantage of the features of the double-gate technology, which allows an input capacitance of only ~35fF. The measured single stage-latch reaches rail-to-rail logic levels with less than 100mV differential input signal and about 10V input common mode range for VDD=20V. The DC small-signal gain is larger than 46dB and the static power dissipation is ~30nW. All measurements were taken in air and in daylight.
Original language | English |
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Title of host publication | Proceedings of the 38th European Solid-State Circuits Conference (ESSCIRC '12), 17-21 September 2012, Bordeaux, France |
Place of Publication | Piscataway |
Publisher | Institute of Electrical and Electronics Engineers |
Pages | 141-144 |
ISBN (Print) | 978-1-4673-3085-5 |
DOIs | |
Publication status | Published - 2012 |
Event | 38th European Solid-State Circuits Conference (ESSCIRC 2012) - Bordeaux Convention Center, Bordeaux, France Duration: 17 Sept 2012 → 21 Sept 2012 Conference number: 38 |
Conference
Conference | 38th European Solid-State Circuits Conference (ESSCIRC 2012) |
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Abbreviated title | ESSCIRC 2012 |
Country/Territory | France |
City | Bordeaux |
Period | 17/09/12 → 21/09/12 |