A spot-defect to fault collapsing technique

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Abstract

A new technique is presented that is capable of collapsing defects to circuit faults by establishing a simple probabilistic model between them. This way of modeling supplies accurate results for ranking the failure probability of nodes and the probability of occurrence of faults. Since it is independent of the multilayer critical area extraction, the collapsing and its related applications can be done effectively in a rather short CPU time. By applying this technique, the likelihood of occurrence of faults, induced by defects, can be ranked accurately according to the conditions prevailing in the manufacturing line. The derivation of the weighted spectrums of nodes, or partial faults, can further be used for manufacturing debugging. The results of the analysis show that conventional testing methods concentrating on single stuck-at faults are insufficient and that, in particular, multiple faults need more careful treatment
Original languageEnglish
Title of host publicationProceedings of the 33rd Midwest Symposium on Circuits and Systems, 1990, 12-14 August 1990, Calgary, Altamont
Place of PublicationPiscataway
PublisherInstitute of Electrical and Electronics Engineers
Pages580-583
ISBN (Print)0-7803-0081-5
DOIs
Publication statusPublished - 1990

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