A single-rail re-implementation of a DCC error detector using a generic standard-cell library

Kees van Berkel; Ronan Burgess; Joep Kessels; Ad Peeters; Marly Roncken; Frits Schalij; Rik van de Wiel

doi:10.1109/WCADM.1995.514644

A single-rail re-implementation of a DCC error detector using a generic standard-cell library

Kees van Berkel, Ronan Burgess, Joep Kessels, Ad Peeters, Marly Roncken, Frits Schalij, Rik van de Wiel

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › Academic › peer-review

27 Citations (Scopus)

Abstract

We present a fully asynchronous implementation of a DCC Error Detector. The circuit uses 4-phase handshake signaling and single-rail data encoding, and has been realized using standard cells from a generic cell library. The circuit is obtained by fully automatic translation from a high-level (Tangram) description, using handshake circuits as intermediate architecture. In comparison with a previous double-rail implementation the fabricated IC is 40% smaller (core area), three times faster, and consumes only a quarter of the power. Switching between two power supplies is described as a technique to reduce power dissipation even further. A comparative evaluation also includes an improved double-rail implementation and two synchronous circuits.

Original language	English
Title of host publication	Second Working Conference on Asynchronous Design Methodologies
Publisher	Institute of Electrical and Electronics Engineers
Pages	72-79
Number of pages	8
ISBN (Print)	0-8186-7098-3
DOIs	https://doi.org/10.1109/WCADM.1995.514644
Publication status	Published - 1995
Externally published	Yes
Event	2nd Working Conference on Asynchronous Design Methodologies - London, United Kingdom Duration: 30 May 1995 → 31 May 1995

Conference

Conference	2nd Working Conference on Asynchronous Design Methodologies
Country/Territory	United Kingdom
City	London
Period	30/05/95 → 31/05/95

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10.1109/WCADM.1995.514644

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van Berkel, K., Burgess, R., Kessels, J., Peeters, A., Roncken, M., Schalij, F., & van de Wiel, R. (1995). A single-rail re-implementation of a DCC error detector using a generic standard-cell library. In Second Working Conference on Asynchronous Design Methodologies (pp. 72-79). Institute of Electrical and Electronics Engineers. https://doi.org/10.1109/WCADM.1995.514644

@inproceedings{1a6c987c6be74ca1ab60ab39d0cae368,

title = "A single-rail re-implementation of a DCC error detector using a generic standard-cell library",

abstract = "We present a fully asynchronous implementation of a DCC Error Detector. The circuit uses 4-phase handshake signaling and single-rail data encoding, and has been realized using standard cells from a generic cell library. The circuit is obtained by fully automatic translation from a high-level (Tangram) description, using handshake circuits as intermediate architecture. In comparison with a previous double-rail implementation the fabricated IC is 40% smaller (core area), three times faster, and consumes only a quarter of the power. Switching between two power supplies is described as a technique to reduce power dissipation even further. A comparative evaluation also includes an improved double-rail implementation and two synchronous circuits.",

author = "{van Berkel}, Kees and Ronan Burgess and Joep Kessels and Ad Peeters and Marly Roncken and Frits Schalij and {van de Wiel}, Rik",

year = "1995",

doi = "10.1109/WCADM.1995.514644",

language = "English",

isbn = "0-8186-7098-3",

pages = "72--79",

booktitle = "Second Working Conference on Asynchronous Design Methodologies",

publisher = "Institute of Electrical and Electronics Engineers",

address = "United States",

note = "2nd Working Conference on Asynchronous Design Methodologies ; Conference date: 30-05-1995 Through 31-05-1995",

}

van Berkel, K, Burgess, R, Kessels, J, Peeters, A, Roncken, M, Schalij, F & van de Wiel, R 1995, A single-rail re-implementation of a DCC error detector using a generic standard-cell library. in Second Working Conference on Asynchronous Design Methodologies. Institute of Electrical and Electronics Engineers, pp. 72-79, 2nd Working Conference on Asynchronous Design Methodologies, London, United Kingdom, 30/05/95. https://doi.org/10.1109/WCADM.1995.514644

A single-rail re-implementation of a DCC error detector using a generic standard-cell library. / van Berkel, Kees; Burgess, Ronan; Kessels, Joep et al.
Second Working Conference on Asynchronous Design Methodologies. Institute of Electrical and Electronics Engineers, 1995. p. 72-79.

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › Academic › peer-review

TY - GEN

T1 - A single-rail re-implementation of a DCC error detector using a generic standard-cell library

AU - van Berkel, Kees

AU - Burgess, Ronan

AU - Kessels, Joep

AU - Peeters, Ad

AU - Roncken, Marly

AU - Schalij, Frits

AU - van de Wiel, Rik

PY - 1995

Y1 - 1995

N2 - We present a fully asynchronous implementation of a DCC Error Detector. The circuit uses 4-phase handshake signaling and single-rail data encoding, and has been realized using standard cells from a generic cell library. The circuit is obtained by fully automatic translation from a high-level (Tangram) description, using handshake circuits as intermediate architecture. In comparison with a previous double-rail implementation the fabricated IC is 40% smaller (core area), three times faster, and consumes only a quarter of the power. Switching between two power supplies is described as a technique to reduce power dissipation even further. A comparative evaluation also includes an improved double-rail implementation and two synchronous circuits.

AB - We present a fully asynchronous implementation of a DCC Error Detector. The circuit uses 4-phase handshake signaling and single-rail data encoding, and has been realized using standard cells from a generic cell library. The circuit is obtained by fully automatic translation from a high-level (Tangram) description, using handshake circuits as intermediate architecture. In comparison with a previous double-rail implementation the fabricated IC is 40% smaller (core area), three times faster, and consumes only a quarter of the power. Switching between two power supplies is described as a technique to reduce power dissipation even further. A comparative evaluation also includes an improved double-rail implementation and two synchronous circuits.

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U2 - 10.1109/WCADM.1995.514644

DO - 10.1109/WCADM.1995.514644

M3 - Conference contribution

AN - SCOPUS:0029213957

SN - 0-8186-7098-3

SP - 72

EP - 79

BT - Second Working Conference on Asynchronous Design Methodologies

PB - Institute of Electrical and Electronics Engineers

T2 - 2nd Working Conference on Asynchronous Design Methodologies

Y2 - 30 May 1995 through 31 May 1995

ER -

A single-rail re-implementation of a DCC error detector using a generic standard-cell library

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