A scalable architecture for LDPC decoding

Mauro Cocco, John Dielissen, Marc Heijligers, Andries Hekstra, Jos Huisken

Research output: Chapter in Book/Report/Conference proceedingConference contributionAcademicpeer-review

22 Citations (Scopus)

Abstract

Low Density Parity Check (LDPC) codes offer excellent error correcting performance. However, current implementations are not capable of achieving the performance required by next generation storage and telecom applications. Extrapolation of many of those designs is not possible because of routing congestions. This article proposes a new architecture, based on a redefinition of a lesser-known LDPC decoding algorithm. As random LDPC codes are the most powerful, we abstain from making simplifying assumptions about the LDPC code which could ease the routing problem. We avoid the routing congestion problem by going for multiple independent sequential decoding machines, each decoding separate received codewords. In this serial approach the required amount of memory must be multiplied by the large number of machines. Our key contribution is a check node centric reformulation of the algorithm which gives huge memory reduction and which thus makes the serial approach possible.

Original languageEnglish
Title of host publicationDesigners Forum - Design, Automation and Test in Europe Conference and Exhibition, DATE 04
EditorsM. Lindwer, V. Gerousis, J. Fifueras
Pages88-93
Number of pages6
DOIs
Publication statusPublished - 12 Jul 2004
Externally publishedYes
Event7th Design, Automation and Test in Europe Conference and Exposition (DATE 2004) - Paris, France
Duration: 16 Feb 200420 Feb 2004
Conference number: 7

Conference

Conference7th Design, Automation and Test in Europe Conference and Exposition (DATE 2004)
Abbreviated titleDATE 2004
Country/TerritoryFrance
CityParis
Period16/02/0420/02/04

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