A sampling problem from lithography for chip layout

E. Cator, T.J. Dijkema, M.E. Hochstenbach, W. Mulckhuyse, M.A. Peletier, G. Prokert, W. Weij, van der, D. Worm

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Abstract

Given a list with simple polygons and a sampling grid geometry, we calculate the sample (greyscale) value of each grid pixel, such that the residual error in a certain norm is sufficiently small, taking into account that the amount of computational operations should be minimal.
Original languageEnglish
Title of host publicationProceedings 58th European Study Group Mathematics with Industry (ESGI58/SWI2007), 29 January - 2 February 2007, Utrecht, The Netherlands
EditorsR.H. Bisseling, K. Dajani, T.J. Dijkema, J. Leur, van de, P.A. Zegeling
Place of PublicationUtrecht
PublisherUtrecht University
Pages45-53
Publication statusPublished - 2007

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