A reconfigurable ray-tracing multi-processor SoC with hardware replication-aware instruction set extension

F.M.G. Franca, A.S. Nery, N. Nedjah, L. Jozwiak, H. Corporaal

Research output: Chapter in Book/Report/Conference proceedingConference contributionAcademicpeer-review

1 Citation (Scopus)


Application code and processor parallelization, together with instruction set customization, are the most common and effective ways to enhance the performance and efficiency of application-specific processors (ASIPs). Both the effective code parallelization and data/task parallelism exploitation, as well as effective instruction set customization, enable an ASIP to achieve a significant performance improvement using limited extra hardware resources. However, a naive parallelization or instruction set customization may not result in the required performance improvement, leading to a waste of computing and energy resources. Therefore, when performing parallelization or custom instruction selection, complex tradeoffs between processing speed, circuit area and power consumption must be closely observed. In this paper, we propose and discuss an efficient ASIP-based Multi-Processor System-on-a-Chip (MPSoC) design for ray-tracing, exploiting application parallelism and hardware replication-aware instruction set customization. Without hardware sharing among the custom instructions units, the proposed parallel ray-tracer MPSoC design with custom instructions achieves 77% speed up in comparison to a single microprocessor design with the default instruction set. However, with the replication-aware instruction set customization, the speed up increases to 81%.
Original languageEnglish
Title of host publication13th International Conference on Algorithms and Architectures for Parallel Processing (ICA3PP), Vietri sul Mare, Italy, December 18-20, 2013, Proceedings, Part I
Place of PublicationBerlin
ISBN (Print)978-3-319-03859-9
Publication statusPublished - 2013


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